Re: [PATCHv3 5/8] ARM: dts: Add memory bus node for Exynos4x12

This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has two memory bus to translate data between DRAM and eMMC/sub-IPs. Following list specifies the detailed relation between memory bus clock and DMC IP in MIF (Memory Interface) block: - DMC/ACP clock : DMC

[PATCHv3 5/8] ARM: dts: Add memory bus node for Exynos4x12

This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has two memory bus to translate data between DRAM and eMMC/sub-IPs. Following list specifies the detailed relation between memory bus clock and DMC IP in MIF (Memory Interface) block: - DMC/ACP clock : DMC (Dynamic Memory