Re: [PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-19 Thread Chanwoo Choi 
Hi Tomasz,

On 06/18/2014 04:55 PM, Tomasz Figa wrote:
 Hi Chanwoo,
 
 On 18.06.2014 04:20, Chanwoo Choi wrote:
 This patchset add 'exynos_adc_ops' structure which includes some functions
 to control ADC operation according to ADC version (v1 or v2).

 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  drivers/iio/adc/exynos_adc.c | 174 
 +--
  1 file changed, 120 insertions(+), 54 deletions(-)

 diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
 index 010578f..c30def6 100644
 --- a/drivers/iio/adc/exynos_adc.c
 +++ b/drivers/iio/adc/exynos_adc.c
 @@ -90,6 +90,7 @@ struct exynos_adc {
  struct clk  *clk;
  unsigned intirq;
  struct regulator*vdd;
 +struct exynos_adc_ops   *ops;
  
  struct completion   completion;
  
 @@ -97,6 +98,13 @@ struct exynos_adc {
  unsigned intversion;
  };
  
 +struct exynos_adc_ops {
 +void (*init_hw)(struct exynos_adc *info);
 +void (*clear_irq)(struct exynos_adc *info);
 +void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 +void (*stop_conv)(struct exynos_adc *info);
 +};
 +
  static const struct of_device_id exynos_adc_match[] = {
  { .compatible = samsung,exynos-adc-v1, .data = (void *)ADC_V1 },
  { .compatible = samsung,exynos-adc-v2, .data = (void *)ADC_V2 },
 @@ -112,30 +120,98 @@ static inline unsigned int 
 exynos_adc_get_version(struct platform_device *pdev)
  return (unsigned int)match-data;
  }
  
 -static void exynos_adc_hw_init(struct exynos_adc *info)
 +static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 +{
 +u32 con1;
 +
 +/* set default prescaler values and Enable prescaler */
 +con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +
 +/* Enable 12-bit ADC resolution */
 +con1 |= ADC_V1_CON_RES;
 +writel(con1, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 +u32 con1;
 +
 +writel(addr, ADC_V1_MUX(info-regs));
 +
 +con1 = readl(ADC_V1_CON(info-regs));
 +writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 +{
 +writel(1, ADC_V1_INTCLR(info-regs));
 +}
 +
 +static void exynos_adc_v1_stop_conv(struct exynos_adc *info)
 +{
 +u32 con;
 +
 +con = readl(ADC_V1_CON(info-regs));
 +con |= ADC_V1_CON_STANDBY;
 +writel(con, ADC_V1_CON(info-regs));
 +}
 +
 +static struct exynos_adc_ops exynos_adc_v1_ops = {
 +.init_hw= exynos_adc_v1_init_hw,
 +.clear_irq  = exynos_adc_v1_clear_irq,
 +.start_conv = exynos_adc_v1_start_conv,
 +.stop_conv  = exynos_adc_v1_stop_conv,
 +};
 +
 +static void exynos_adc_v2_init_hw(struct exynos_adc *info)
  {
  u32 con1, con2;
  
 -if (info-version == ADC_V2) {
 -con1 = ADC_V2_CON1_SOFT_RESET;
 -writel(con1, ADC_V2_CON1(info-regs));
 +con1 = ADC_V2_CON1_SOFT_RESET;
 +writel(con1, ADC_V2_CON1(info-regs));
  
 -con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 -ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 -writel(con2, ADC_V2_CON2(info-regs));
 +con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 +ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 +writel(con2, ADC_V2_CON2(info-regs));
  
 -/* Enable interrupts */
 -writel(1, ADC_V2_INT_EN(info-regs));
 -} else {
 -/* set default prescaler values and Enable prescaler */
 -con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +/* Enable interrupts */
 +writel(1, ADC_V2_INT_EN(info-regs));
 +}
  
 -/* Enable 12-bit ADC resolution */
 -con1 |= ADC_V1_CON_RES;
 -writel(con1, ADC_V1_CON(info-regs));
 -}
 +static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 +u32 con1, con2;
 +
 +con2 = readl(ADC_V2_CON2(info-regs));
 +con2 = ~ADC_V2_CON2_ACH_MASK;
 +con2 |= ADC_V2_CON2_ACH_SEL(addr);
 +writel(con2, ADC_V2_CON2(info-regs));
 +
 +con1 = readl(ADC_V2_CON1(info-regs));
 +writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info-regs));
 +}
 +
 +static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 +{
 +writel(1, ADC_V2_INT_ST(info-regs));
 +}
 +
 +static void exynos_adc_v2_stop_conv(struct exynos_adc *info)
 +{
 +u32 con;
 +
 +con = readl(ADC_V2_CON1(info-regs));
 +con = ~ADC_CON_EN_START;
 +writel(con, ADC_V2_CON1(info-regs));
  }
  
 +static struct exynos_adc_ops exynos_adc_v2_ops = {
 +.init_hw= exynos_adc_v2_init_hw,
 +.start_conv = exynos_adc_v2_start_conv,
 +.clear_irq  = exynos_adc_v2_clear_irq,
 +.stop_conv  = exynos_adc_v2_stop_conv,
 +};
 +
  static int exynos_read_raw(struct iio_dev *indio_dev,

Re: [PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-19 Thread Tomasz Figa 
On 20.06.2014 02:20, Chanwoo Choi wrote:
 Hi Tomasz,
 
 On 06/18/2014 04:55 PM, Tomasz Figa wrote:
 Hi Chanwoo,

 On 18.06.2014 04:20, Chanwoo Choi wrote:
 This patchset add 'exynos_adc_ops' structure which includes some functions
 to control ADC operation according to ADC version (v1 or v2).

 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  drivers/iio/adc/exynos_adc.c | 174 
 +--
  1 file changed, 120 insertions(+), 54 deletions(-)

 diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
 index 010578f..c30def6 100644
 --- a/drivers/iio/adc/exynos_adc.c
 +++ b/drivers/iio/adc/exynos_adc.c
 @@ -90,6 +90,7 @@ struct exynos_adc {
 struct clk  *clk;
 unsigned intirq;
 struct regulator*vdd;
 +   struct exynos_adc_ops   *ops;
  
 struct completion   completion;
  
 @@ -97,6 +98,13 @@ struct exynos_adc {
 unsigned intversion;
  };
  
 +struct exynos_adc_ops {
 +   void (*init_hw)(struct exynos_adc *info);
 +   void (*clear_irq)(struct exynos_adc *info);
 +   void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 +   void (*stop_conv)(struct exynos_adc *info);
 +};
 +
  static const struct of_device_id exynos_adc_match[] = {
 { .compatible = samsung,exynos-adc-v1, .data = (void *)ADC_V1 },
 { .compatible = samsung,exynos-adc-v2, .data = (void *)ADC_V2 },
 @@ -112,30 +120,98 @@ static inline unsigned int 
 exynos_adc_get_version(struct platform_device *pdev)
 return (unsigned int)match-data;
  }
  
 -static void exynos_adc_hw_init(struct exynos_adc *info)
 +static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 +{
 +   u32 con1;
 +
 +   /* set default prescaler values and Enable prescaler */
 +   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +
 +   /* Enable 12-bit ADC resolution */
 +   con1 |= ADC_V1_CON_RES;
 +   writel(con1, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_start_conv(struct exynos_adc *info, unsigned 
 long addr)
 +{
 +   u32 con1;
 +
 +   writel(addr, ADC_V1_MUX(info-regs));
 +
 +   con1 = readl(ADC_V1_CON(info-regs));
 +   writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 +{
 +   writel(1, ADC_V1_INTCLR(info-regs));
 +}
 +
 +static void exynos_adc_v1_stop_conv(struct exynos_adc *info)
 +{
 +   u32 con;
 +
 +   con = readl(ADC_V1_CON(info-regs));
 +   con |= ADC_V1_CON_STANDBY;
 +   writel(con, ADC_V1_CON(info-regs));
 +}
 +
 +static struct exynos_adc_ops exynos_adc_v1_ops = {
 +   .init_hw= exynos_adc_v1_init_hw,
 +   .clear_irq  = exynos_adc_v1_clear_irq,
 +   .start_conv = exynos_adc_v1_start_conv,
 +   .stop_conv  = exynos_adc_v1_stop_conv,
 +};
 +
 +static void exynos_adc_v2_init_hw(struct exynos_adc *info)
  {
 u32 con1, con2;
  
 -   if (info-version == ADC_V2) {
 -   con1 = ADC_V2_CON1_SOFT_RESET;
 -   writel(con1, ADC_V2_CON1(info-regs));
 +   con1 = ADC_V2_CON1_SOFT_RESET;
 +   writel(con1, ADC_V2_CON1(info-regs));
  
 -   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 -   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 -   writel(con2, ADC_V2_CON2(info-regs));
 +   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 +   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 +   writel(con2, ADC_V2_CON2(info-regs));
  
 -   /* Enable interrupts */
 -   writel(1, ADC_V2_INT_EN(info-regs));
 -   } else {
 -   /* set default prescaler values and Enable prescaler */
 -   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +   /* Enable interrupts */
 +   writel(1, ADC_V2_INT_EN(info-regs));
 +}
  
 -   /* Enable 12-bit ADC resolution */
 -   con1 |= ADC_V1_CON_RES;
 -   writel(con1, ADC_V1_CON(info-regs));
 -   }
 +static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned 
 long addr)
 +{
 +   u32 con1, con2;
 +
 +   con2 = readl(ADC_V2_CON2(info-regs));
 +   con2 = ~ADC_V2_CON2_ACH_MASK;
 +   con2 |= ADC_V2_CON2_ACH_SEL(addr);
 +   writel(con2, ADC_V2_CON2(info-regs));
 +
 +   con1 = readl(ADC_V2_CON1(info-regs));
 +   writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info-regs));
 +}
 +
 +static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 +{
 +   writel(1, ADC_V2_INT_ST(info-regs));
 +}
 +
 +static void exynos_adc_v2_stop_conv(struct exynos_adc *info)
 +{
 +   u32 con;
 +
 +   con = readl(ADC_V2_CON1(info-regs));
 +   con = ~ADC_CON_EN_START;
 +   writel(con, ADC_V2_CON1(info-regs));
  }
  
 +static struct exynos_adc_ops exynos_adc_v2_ops = {
 +   .init_hw= exynos_adc_v2_init_hw,
 +   .start_conv = exynos_adc_v2_start_conv,
 +   .clear_irq  = exynos_adc_v2_clear_irq,
 +   .stop_conv  = exynos_adc_v2_stop_conv,
 +};
 +
  static int exynos_read_raw(struct iio_dev *indio_dev,
 struct iio_chan_spec const

Re: [PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-18 Thread Tomasz Figa 
Hi Chanwoo,

On 18.06.2014 04:20, Chanwoo Choi wrote:
 This patchset add 'exynos_adc_ops' structure which includes some functions
 to control ADC operation according to ADC version (v1 or v2).
 
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 ---
  drivers/iio/adc/exynos_adc.c | 174 
 +--
  1 file changed, 120 insertions(+), 54 deletions(-)
 
 diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
 index 010578f..c30def6 100644
 --- a/drivers/iio/adc/exynos_adc.c
 +++ b/drivers/iio/adc/exynos_adc.c
 @@ -90,6 +90,7 @@ struct exynos_adc {
   struct clk  *clk;
   unsigned intirq;
   struct regulator*vdd;
 + struct exynos_adc_ops   *ops;
  
   struct completion   completion;
  
 @@ -97,6 +98,13 @@ struct exynos_adc {
   unsigned intversion;
  };
  
 +struct exynos_adc_ops {
 + void (*init_hw)(struct exynos_adc *info);
 + void (*clear_irq)(struct exynos_adc *info);
 + void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 + void (*stop_conv)(struct exynos_adc *info);
 +};
 +
  static const struct of_device_id exynos_adc_match[] = {
   { .compatible = samsung,exynos-adc-v1, .data = (void *)ADC_V1 },
   { .compatible = samsung,exynos-adc-v2, .data = (void *)ADC_V2 },
 @@ -112,30 +120,98 @@ static inline unsigned int 
 exynos_adc_get_version(struct platform_device *pdev)
   return (unsigned int)match-data;
  }
  
 -static void exynos_adc_hw_init(struct exynos_adc *info)
 +static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 +{
 + u32 con1;
 +
 + /* set default prescaler values and Enable prescaler */
 + con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +
 + /* Enable 12-bit ADC resolution */
 + con1 |= ADC_V1_CON_RES;
 + writel(con1, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 + u32 con1;
 +
 + writel(addr, ADC_V1_MUX(info-regs));
 +
 + con1 = readl(ADC_V1_CON(info-regs));
 + writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 +{
 + writel(1, ADC_V1_INTCLR(info-regs));
 +}
 +
 +static void exynos_adc_v1_stop_conv(struct exynos_adc *info)
 +{
 + u32 con;
 +
 + con = readl(ADC_V1_CON(info-regs));
 + con |= ADC_V1_CON_STANDBY;
 + writel(con, ADC_V1_CON(info-regs));
 +}
 +
 +static struct exynos_adc_ops exynos_adc_v1_ops = {
 + .init_hw= exynos_adc_v1_init_hw,
 + .clear_irq  = exynos_adc_v1_clear_irq,
 + .start_conv = exynos_adc_v1_start_conv,
 + .stop_conv  = exynos_adc_v1_stop_conv,
 +};
 +
 +static void exynos_adc_v2_init_hw(struct exynos_adc *info)
  {
   u32 con1, con2;
  
 - if (info-version == ADC_V2) {
 - con1 = ADC_V2_CON1_SOFT_RESET;
 - writel(con1, ADC_V2_CON1(info-regs));
 + con1 = ADC_V2_CON1_SOFT_RESET;
 + writel(con1, ADC_V2_CON1(info-regs));
  
 - con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 - ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 - writel(con2, ADC_V2_CON2(info-regs));
 + con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 + ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 + writel(con2, ADC_V2_CON2(info-regs));
  
 - /* Enable interrupts */
 - writel(1, ADC_V2_INT_EN(info-regs));
 - } else {
 - /* set default prescaler values and Enable prescaler */
 - con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 + /* Enable interrupts */
 + writel(1, ADC_V2_INT_EN(info-regs));
 +}
  
 - /* Enable 12-bit ADC resolution */
 - con1 |= ADC_V1_CON_RES;
 - writel(con1, ADC_V1_CON(info-regs));
 - }
 +static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 + u32 con1, con2;
 +
 + con2 = readl(ADC_V2_CON2(info-regs));
 + con2 = ~ADC_V2_CON2_ACH_MASK;
 + con2 |= ADC_V2_CON2_ACH_SEL(addr);
 + writel(con2, ADC_V2_CON2(info-regs));
 +
 + con1 = readl(ADC_V2_CON1(info-regs));
 + writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info-regs));
 +}
 +
 +static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 +{
 + writel(1, ADC_V2_INT_ST(info-regs));
 +}
 +
 +static void exynos_adc_v2_stop_conv(struct exynos_adc *info)
 +{
 + u32 con;
 +
 + con = readl(ADC_V2_CON1(info-regs));
 + con = ~ADC_CON_EN_START;
 + writel(con, ADC_V2_CON1(info-regs));
  }
  
 +static struct exynos_adc_ops exynos_adc_v2_ops = {
 + .init_hw= exynos_adc_v2_init_hw,
 + .start_conv = exynos_adc_v2_start_conv,
 + .clear_irq  = exynos_adc_v2_clear_irq,
 + .stop_conv  = exynos_adc_v2_stop_conv,
 +};
 +
  static int exynos_read_raw(struct iio_dev *indio_dev,

[PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-17 Thread Chanwoo Choi 
This patchset add 'exynos_adc_ops' structure which includes some functions
to control ADC operation according to ADC version (v1 or v2).

Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
 drivers/iio/adc/exynos_adc.c | 174 +--
 1 file changed, 120 insertions(+), 54 deletions(-)

diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 010578f..c30def6 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -90,6 +90,7 @@ struct exynos_adc {
struct clk  *clk;
unsigned intirq;
struct regulator*vdd;
+   struct exynos_adc_ops   *ops;
 
struct completion   completion;
 
@@ -97,6 +98,13 @@ struct exynos_adc {
unsigned intversion;
 };
 
+struct exynos_adc_ops {
+   void (*init_hw)(struct exynos_adc *info);
+   void (*clear_irq)(struct exynos_adc *info);
+   void (*start_conv)(struct exynos_adc *info, unsigned long addr);
+   void (*stop_conv)(struct exynos_adc *info);
+};
+
 static const struct of_device_id exynos_adc_match[] = {
{ .compatible = samsung,exynos-adc-v1, .data = (void *)ADC_V1 },
{ .compatible = samsung,exynos-adc-v2, .data = (void *)ADC_V2 },
@@ -112,30 +120,98 @@ static inline unsigned int exynos_adc_get_version(struct 
platform_device *pdev)
return (unsigned int)match-data;
 }
 
-static void exynos_adc_hw_init(struct exynos_adc *info)
+static void exynos_adc_v1_init_hw(struct exynos_adc *info)
+{
+   u32 con1;
+
+   /* set default prescaler values and Enable prescaler */
+   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
+
+   /* Enable 12-bit ADC resolution */
+   con1 |= ADC_V1_CON_RES;
+   writel(con1, ADC_V1_CON(info-regs));
+}
+
+static void exynos_adc_v1_start_conv(struct exynos_adc *info, unsigned long 
addr)
+{
+   u32 con1;
+
+   writel(addr, ADC_V1_MUX(info-regs));
+
+   con1 = readl(ADC_V1_CON(info-regs));
+   writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info-regs));
+}
+
+static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
+{
+   writel(1, ADC_V1_INTCLR(info-regs));
+}
+
+static void exynos_adc_v1_stop_conv(struct exynos_adc *info)
+{
+   u32 con;
+
+   con = readl(ADC_V1_CON(info-regs));
+   con |= ADC_V1_CON_STANDBY;
+   writel(con, ADC_V1_CON(info-regs));
+}
+
+static struct exynos_adc_ops exynos_adc_v1_ops = {
+   .init_hw= exynos_adc_v1_init_hw,
+   .clear_irq  = exynos_adc_v1_clear_irq,
+   .start_conv = exynos_adc_v1_start_conv,
+   .stop_conv  = exynos_adc_v1_stop_conv,
+};
+
+static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 {
u32 con1, con2;
 
-   if (info-version == ADC_V2) {
-   con1 = ADC_V2_CON1_SOFT_RESET;
-   writel(con1, ADC_V2_CON1(info-regs));
+   con1 = ADC_V2_CON1_SOFT_RESET;
+   writel(con1, ADC_V2_CON1(info-regs));
 
-   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
-   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
-   writel(con2, ADC_V2_CON2(info-regs));
+   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
+   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
+   writel(con2, ADC_V2_CON2(info-regs));
 
-   /* Enable interrupts */
-   writel(1, ADC_V2_INT_EN(info-regs));
-   } else {
-   /* set default prescaler values and Enable prescaler */
-   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
+   /* Enable interrupts */
+   writel(1, ADC_V2_INT_EN(info-regs));
+}
 
-   /* Enable 12-bit ADC resolution */
-   con1 |= ADC_V1_CON_RES;
-   writel(con1, ADC_V1_CON(info-regs));
-   }
+static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned long 
addr)
+{
+   u32 con1, con2;
+
+   con2 = readl(ADC_V2_CON2(info-regs));
+   con2 = ~ADC_V2_CON2_ACH_MASK;
+   con2 |= ADC_V2_CON2_ACH_SEL(addr);
+   writel(con2, ADC_V2_CON2(info-regs));
+
+   con1 = readl(ADC_V2_CON1(info-regs));
+   writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info-regs));
+}
+
+static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
+{
+   writel(1, ADC_V2_INT_ST(info-regs));
+}
+
+static void exynos_adc_v2_stop_conv(struct exynos_adc *info)
+{
+   u32 con;
+
+   con = readl(ADC_V2_CON1(info-regs));
+   con = ~ADC_CON_EN_START;
+   writel(con, ADC_V2_CON1(info-regs));
 }
 
+static struct exynos_adc_ops exynos_adc_v2_ops = {
+   .init_hw= exynos_adc_v2_init_hw,
+   .start_conv = exynos_adc_v2_start_conv,
+   .clear_irq  = exynos_adc_v2_clear_irq,
+   .stop_conv  = exynos_adc_v2_stop_conv,
+};
+
 static int exynos_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,

Re: [PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-17 Thread Naveen Krishna Ch 
Hello Chanwoo,

On 18 June 2014 07:50, Chanwoo Choi cw00.c...@samsung.com wrote:
 This patchset add 'exynos_adc_ops' structure which includes some functions
 to control ADC operation according to ADC version (v1 or v2).

 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com

This is a good piece of change, Thanks.

Reviewed-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
 ---
  drivers/iio/adc/exynos_adc.c | 174 
 +--
  1 file changed, 120 insertions(+), 54 deletions(-)

 diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
 index 010578f..c30def6 100644
 --- a/drivers/iio/adc/exynos_adc.c
 +++ b/drivers/iio/adc/exynos_adc.c
 @@ -90,6 +90,7 @@ struct exynos_adc {
 struct clk  *clk;
 unsigned intirq;
 struct regulator*vdd;
 +   struct exynos_adc_ops   *ops;

 struct completion   completion;

 @@ -97,6 +98,13 @@ struct exynos_adc {
 unsigned intversion;
  };

 +struct exynos_adc_ops {
 +   void (*init_hw)(struct exynos_adc *info);
 +   void (*clear_irq)(struct exynos_adc *info);
 +   void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 +   void (*stop_conv)(struct exynos_adc *info);
 +};
 +
  static const struct of_device_id exynos_adc_match[] = {
 { .compatible = samsung,exynos-adc-v1, .data = (void *)ADC_V1 },
 { .compatible = samsung,exynos-adc-v2, .data = (void *)ADC_V2 },
 @@ -112,30 +120,98 @@ static inline unsigned int 
 exynos_adc_get_version(struct platform_device *pdev)
 return (unsigned int)match-data;
  }

 -static void exynos_adc_hw_init(struct exynos_adc *info)
 +static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 +{
 +   u32 con1;
 +
 +   /* set default prescaler values and Enable prescaler */
 +   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +
 +   /* Enable 12-bit ADC resolution */
 +   con1 |= ADC_V1_CON_RES;
 +   writel(con1, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 +   u32 con1;
 +
 +   writel(addr, ADC_V1_MUX(info-regs));
 +
 +   con1 = readl(ADC_V1_CON(info-regs));
 +   writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info-regs));
 +}
 +
 +static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 +{
 +   writel(1, ADC_V1_INTCLR(info-regs));
 +}
 +
 +static void exynos_adc_v1_stop_conv(struct exynos_adc *info)
 +{
 +   u32 con;
 +
 +   con = readl(ADC_V1_CON(info-regs));
 +   con |= ADC_V1_CON_STANDBY;
 +   writel(con, ADC_V1_CON(info-regs));
 +}
 +
 +static struct exynos_adc_ops exynos_adc_v1_ops = {
 +   .init_hw= exynos_adc_v1_init_hw,
 +   .clear_irq  = exynos_adc_v1_clear_irq,
 +   .start_conv = exynos_adc_v1_start_conv,
 +   .stop_conv  = exynos_adc_v1_stop_conv,
 +};
 +
 +static void exynos_adc_v2_init_hw(struct exynos_adc *info)
  {
 u32 con1, con2;

 -   if (info-version == ADC_V2) {
 -   con1 = ADC_V2_CON1_SOFT_RESET;
 -   writel(con1, ADC_V2_CON1(info-regs));
 +   con1 = ADC_V2_CON1_SOFT_RESET;
 +   writel(con1, ADC_V2_CON1(info-regs));

 -   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 -   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 -   writel(con2, ADC_V2_CON2(info-regs));
 +   con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 +   ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 +   writel(con2, ADC_V2_CON2(info-regs));

 -   /* Enable interrupts */
 -   writel(1, ADC_V2_INT_EN(info-regs));
 -   } else {
 -   /* set default prescaler values and Enable prescaler */
 -   con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 +   /* Enable interrupts */
 +   writel(1, ADC_V2_INT_EN(info-regs));
 +}

 -   /* Enable 12-bit ADC resolution */
 -   con1 |= ADC_V1_CON_RES;
 -   writel(con1, ADC_V1_CON(info-regs));
 -   }
 +static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned long 
 addr)
 +{
 +   u32 con1, con2;
 +
 +   con2 = readl(ADC_V2_CON2(info-regs));
 +   con2 = ~ADC_V2_CON2_ACH_MASK;
 +   con2 |= ADC_V2_CON2_ACH_SEL(addr);
 +   writel(con2, ADC_V2_CON2(info-regs));
 +
 +   con1 = readl(ADC_V2_CON1(info-regs));
 +   writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info-regs));
 +}
 +
 +static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 +{
 +   writel(1, ADC_V2_INT_ST(info-regs));
 +}
 +
 +static void exynos_adc_v2_stop_conv(struct exynos_adc *info)
 +{
 +   u32 con;
 +
 +   con = readl(ADC_V2_CON1(info-regs));
 +   con = ~ADC_CON_EN_START;
 +   writel(con, ADC_V2_CON1(info-regs));
  }

 +static struct exynos_adc_ops exynos_adc_v2_ops = {
 +   .init_hw=

Re: [PATCHv4 1/4] iio: adc: exynos_adc: Add exynos_adc_ops structure to improve readability

2014-06-17 Thread Chanwoo Choi 
Hi Naveen,

On 06/18/2014 02:27 PM, Naveen Krishna Ch wrote:
 Hello Chanwoo,
 
 On 18 June 2014 07:50, Chanwoo Choi cw00.c...@samsung.com wrote:
 This patchset add 'exynos_adc_ops' structure which includes some functions
 to control ADC operation according to ADC version (v1 or v2).

 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com
 
 This is a good piece of change, Thanks.
 
 Reviewed-by: Naveen Krishna Chatradhi ch.nav...@samsung.com

Thanks for your review.

Best Regards,
Chanwoo Choi
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