Hi,
2012/6/21 Kukjin Kim kgene@samsung.com:
From: Boojin Kim boojin@samsung.com
Since SYSRAM set the L2 cache latency on EXYNOS5 SoCs,
I don't understand this. Do you mean that BL1 codes do it?
I also wonder how enable L2 cache at the exynos5.
no longer need that in the kernel. It
Joonyoung Shim wrote:
I don't understand this. Do you mean that BL1 codes do it?
I also wonder how enable L2 cache at the exynos5.
Yes, the latency configuration of L2 cache is located on IROM or BL1 code.
It can remove the overhead about cache reset and cache flush.
And, Kernel enables L2
