Hi,
2012/6/21 Kukjin Kim kgene@samsung.com:
From: Boojin Kim boojin@samsung.com
Since SYSRAM set the L2 cache latency on EXYNOS5 SoCs,
I don't understand this. Do you mean that BL1 codes do it?
I also wonder how enable L2 cache at the exynos5.
no longer need that in the kernel. It
Hey Rob and Amit,
On Tue, Jun 26, 2012 at 6:12 AM, Rob Lee rob@linaro.org wrote:
Hey Amit,
I was just re-organizing the imx thermal driver that uses this cpu
cooling interface and noticed a couple of small issues here. If
While rewriting the OMAP BG driver on top of this series I
Joonyoung Shim wrote:
I don't understand this. Do you mean that BL1 codes do it?
I also wonder how enable L2 cache at the exynos5.
Yes, the latency configuration of L2 cache is located on IROM or BL1 code.
It can remove the overhead about cache reset and cache flush.
And, Kernel enables L2
-Original Message-
From: Subash Patel [mailto:subas...@gmail.com]
Sent: Tuesday, June 26, 2012 3:23 AM
To: dri-de...@lists.freedesktop.org; linux-samsung-soc@vger.kernel.org;
linaro-mm-...@lists.linaro.org
Cc: ol...@chromium.org; inki@samsung.com; airl...@redhat.com; Subash
-Original Message-
From: Subash Patel [mailto:subas...@gmail.com]
Sent: Tuesday, June 26, 2012 3:23 AM
To: dri-de...@lists.freedesktop.org; linux-samsung-soc@vger.kernel.org;
linaro-mm-...@lists.linaro.org
Cc: ol...@chromium.org; inki@samsung.com; airl...@redhat.com; Subash
