Hi Daniel,
On 22 April 2014 16:12, Daniel Lezcano daniel.lezc...@linaro.org wrote:
On 04/21/2014 01:49 PM, Chander Kashyap wrote:
Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores.
In order to use generic cpuidle-big-little driver, this patch adds
Exynos5420
specific
On Wed, Apr 23, 2014 at 9:42 AM, Alim Akhtar alim.akh...@gmail.com wrote:
Hi Yuvaraj,
On Mon, Mar 24, 2014 at 10:12 AM, Yuvaraj Kumar yuvaraj...@gmail.com wrote:
On Mon, Mar 24, 2014 at 9:59 AM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Hi, Yuvaraj.
NACK. we can use mmc_of_parese().
On Mon, Apr 14, 2014 at 3:45 AM, Chanwoo Choi cw00.c...@samsung.com wrote:
From: Tomasz Figa t.f...@samsung.com
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional
input/output
ports. There are 23 general
On Tue, Apr 22, 2014 at 05:54:06PM +0200, Daniel Vetter wrote:
On Tue, Apr 22, 2014 at 04:42:20PM +0200, Thierry Reding wrote:
[...]
diff --git a/drivers/gpu/drm/drm_fb_helper.c
b/drivers/gpu/drm/drm_fb_helper.c
[...]
@@ -502,6 +503,33 @@ static void drm_fb_helper_crtc_free(struct
On Tue, Apr 22, 2014 at 08:06:19PM +0530, Ajay kumar wrote:
Hi Thierry,
On Tue, Apr 22, 2014 at 1:49 PM, Thierry Reding thierry.red...@gmail.com
wrote:
On Tue, Apr 22, 2014 at 04:09:11AM +0530, Ajay Kumar wrote:
Most of the panels need an init sequence as mentioned below:
--
On 04/23/2014 04:01 PM, Linus Walleij wrote:
On Mon, Apr 14, 2014 at 3:45 AM, Chanwoo Choi cw00.c...@samsung.com wrote:
From: Tomasz Figa t.f...@samsung.com
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158
On Wed, Apr 23, 2014 at 10:26:20AM +0900, YoungJun Cho wrote:
Hi Andrzej
Thank you for comment.
On 04/22/2014 11:02 PM, Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings
Hi,
On Tue, Apr 22, 2014 at 11:29 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 22 Apr 2014, Vivek Gautam wrote:
On Thu, Apr 10, 2014 at 6:54 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for
On Wed, Apr 23, 2014 at 09:29:15AM +0200, Daniel Vetter wrote:
On Tue, Apr 22, 2014 at 08:06:19PM +0530, Ajay kumar wrote:
Hi Thierry,
On Tue, Apr 22, 2014 at 1:49 PM, Thierry Reding thierry.red...@gmail.com
wrote:
On Tue, Apr 22, 2014 at 04:09:11AM +0530, Ajay Kumar wrote:
Most
In exiting kernel, if DAIFMT flags are set in dai_link and I2S is
set to run in master mode, the I2S clocks are not getting configured
resulting in no output.
Existing code clears the current I2S clock settings during i2s_startup
and requires that the clocks are reconfigured. It then assumes that
On 23 April 2014 01:51, Doug Anderson diand...@chromium.org wrote:
Data errors are completely expected during tuning. Printing them out
is confusing people looking at the kernel logs. They see things like:
[3.613296] dwmmc_exynos 1220.dwmmc0: data error, status 0x0088
...and
On 22 April 2014 16:21, Daniel Lezcano daniel.lezc...@linaro.org wrote:
On 04/21/2014 01:49 PM, Chander Kashyap wrote:
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
Signed-off-by: Chander
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by Sachin Kamat)
Changelog v3:
- Removes optional delay, size properties
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.
Tested on SMDK5420.
This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
Doug Anderson wrote:
From: Olof Johansson o...@lixom.net
Don't unmark the device as suspended until after it's been re-setup.
The main race would be w.r.t. an i2c driver that gets resumed at the same
time (asyncronously), that is allowed to do a transfer since suspended
is set to 0
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To: linux-...@vger.kernel.org;
On Wednesday, April 23, 2014 02:55:50 PM Chander Kashyap wrote:
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.
Tested on SMDK5420.
This patch set depends on:
Tushar Behera wrote:
On 22 April 2014 13:08, Alim Akhtar alim.akh...@gmail.com wrote:
Hi Tushar
On Tue, Apr 22, 2014 at 11:09 AM, Tushar Behera
tushar.beh...@linaro.org wrote:
MAU powerdomain provides clocks for Audio sub-system block. This block
comprises of the I2S audio
Hi YoungJun,
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Changelog v3:
- Moves CPU timings relevant properties from FIMD DT
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
Lee, I don't mind if I apply this and send a pull request to you or I
pull a tag from you with this in - what's easiest for you?
I'm
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To:
Hi,
On Wed, Apr 23, 2014 at 4:27 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf
Anton,
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
In order to avoid adding more duplicate #defines, we also move some
register offset definitions to the mfd driver (and resolve
On Wed, Apr 23, 2014 at 01:34:24PM +0530, Tushar Behera wrote:
In exiting kernel, if DAIFMT flags are set in dai_link and I2S is
set to run in master mode, the I2S clocks are not getting configured
resulting in no output.
Applied, thanks.
signature.asc
Description: Digital signature
Hi Andrzej,
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by
If we weren't given an interrupt we shouldn't tell child devices (like
the tps65090 charger) that they have an interrupt. This is needed so
that we can support polling mode in the tps65090 charger driver.
See also (charger: tps65090: Allow charger module to be used when no
irq).
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
In order to avoid adding more duplicate #defines, we also move some
register offset definitions to the mfd driver (and resolve
The tps65090 regulator allows you to specify how long you want it to
wait before detecting an overcurrent condition. Allow specifying that
through the device tree (or through platform data).
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Hi,
Mike, can you apply this patch? Actually you acked it already [1] but I
forgot to put it in the commit message.
The patch wasn't applied in that time because of multiple concurrent
changes in sec-core drivers.
[1]http://thread.gmane.org/gmane.linux.kernel.samsung-soc/28039/focus=310279
On Wednesday, April 23, 2014 8:06 PM, Vivek Gautam wrote:
On Wednesday, April 23, 2014 7:58 PM, Anton Tikhomirov wrote:
On Wednesday, April 23, 2014 6:52 PM, Vivek Gautam wrote:
On Wednesday, April 23, 2014 6:27 PM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam
On Tue, 22 Apr 2014, Doug Anderson wrote:
This series adds the most critical cros_ec changes for newer boards
using cros_ec. Specifically:
* Fixes timing/locking issues with the previously upstreamed (but
never used upstream) cros_ec_spi driver.
* Updates the cros_ec header file to the
From: David Hendricks dhend...@chromium.org
To avoid spamming the EC we calculate the time between the previous
transfer and the current transfer and force a delay if the time delta
is too small.
However, a small miscalculation causes the delay period to be
far too short. Most noticably
On Tue, 22 Apr 2014, Doug Anderson wrote:
We're adding i2c tunneling to the list of things that goes over
cros_ec. i2c tunneling can be slooow, so increase our deadline to
100ms to account for that.
Signed-off-by: Doug Anderson diand...@chromium.org
Reviewed-by: Simon Glass
On Tue, 22 Apr 2014, Doug Anderson wrote:
On ARM Chromebooks we have a few devices that are accessed by both the
AP (the main Application Processor) and the EC (the Embedded
Controller). These are:
* The battery (sbs-battery).
* The power management unit tps65090.
On the original Samsung
On Tue, 22 Apr 2014, Doug Anderson wrote:
From: Bill Richardson wfric...@chromium.org
This just updates include/linux/mfd/cros_ec_commands.h to match the
latest EC version (which is the One True Source for such things). See
https://chromium.googlesource.com/chromiumos/platform/ec
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for
On Tue, 22 Apr 2014, Doug Anderson wrote:
The cros_ec_spi transfer had two problems with its timeout code:
1. It looked at the timeout even in the case that it found valid data.
2. If the cros_ec_spi code got switched out for a while, it's possible
it could get a timeout after a single
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
EHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for
On Tue, 22 Apr 2014, Doug Anderson wrote:
The main transfer function for cros_ec_spi can be called by more than
one client at a time. Make sure that those clients don't stomp on
each other by locking the bus for the duration of the transfer
function.
Signed-off-by: Doug Anderson
On 04/23/2014 01:34 PM, Laurent Pinchart wrote:
Hi Andrzej,
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog
This patchset adds MFCv8 support to the s5p-mfc driver.
MFCv8 has the same operation sequence as that of v6+, but
there is some shuffling of the registers happened. So to
re-use the exisiting code, register access uses context
variables instead of macros.
The patchset modifies opr_v6 file to use
From: Kiran AVND avnd.ki...@samsung.com
This patch adds variant data and core support for
V8 decoder. This patch also adds the register definition
file for new firmware version v8 for MFC.
Signed-off-by: Kiran AVND avnd.ki...@samsung.com
Signed-off-by: Pawel Osciak posc...@chromium.org
Hi,
On Wed, Apr 2, 2014 at 1:20 PM, Pankaj Dubey pankaj.du...@samsung.com wrote:
From: Young-Gun Jang yg1004.j...@samsung.com
Add support for mapping Exynos Power Management Unit (PMU) base address
from device tree. Code will use existing samsung pmu binding information.
This patch also adds
On 04/23/2014 02:55 PM, Laurent Pinchart wrote:
Hi Andrzej,
On Wednesday 23 April 2014 14:48:31 Andrzej Hajda wrote:
On 04/23/2014 01:34 PM, Laurent Pinchart wrote:
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT
On Wed, Apr 23, 2014 at 09:35:48AM +0200, Daniel Vetter wrote:
On Wed, Apr 23, 2014 at 09:14:41AM +0200, Thierry Reding wrote:
On Tue, Apr 22, 2014 at 05:54:06PM +0200, Daniel Vetter wrote:
On Tue, Apr 22, 2014 at 04:42:20PM +0200, Thierry Reding wrote:
[...]
diff --git
The rtc-s5m driver does not support all of S2M and S5M chipsets
supported by main MFD sec-core driver. For such chipsets unsupported by
rtc-s5m, the MFD sec-core driver initialized regmap with default config.
This config in such cases wouldn't work at all.
The main MFD sec-core driver
Based on 'for-next' branch of Kgene's linux-samsung tree.
Tested with phy-driver[1] patches and peach-pit dts[2].
This is the DT split part of the patch-series[3].
Patches: usb-phy: samsung-usb3: Remove older phy-samsung-usb3 driver
ARM: exynos_defconfig: Remove SAMSUNG_USB3PHY config
Removing this older USB 3.0 DRD controller PHY driver, since
a new driver based on generic phy framework is now available.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
This is reworked version for the patch :
[PATCH V4 5/5] usb-phy:
After removing the phy-samsung-usb3 driver, this config
should be removed.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/configs/exynos_defconfig |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/exynos_defconfig
b/arch/arm/configs/exynos_defconfig
index
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
This is first version of the patch for VBUS support for USB3DRD phy.
v5 is just and indicative of the patch-series.
arch/arm/boot/dts/exynos5420-smdk5420.dts | 46
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
This is first version of the patch for VBUS support for USB3DRD phy.
v5 is just and indicative of the patch-series.
arch/arm/boot/dts/exynos5420-peach-pit.dts |
Removing the dt node for older usb3 phy driver from Exynos5250
device tree and updating the dt node for DWC3 controller to
use new phy driver based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 34 ++
1 file changed,
Add device tree node for new usbdrd-phy driver, which
is based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
On 04/22/2014 01:51 PM, Russell King - ARM Linux wrote:
On Tue, Apr 22, 2014 at 01:29:54PM +0200, Andrzej Hajda wrote:
On 04/18/2014 02:46 PM, Russell King - ARM Linux wrote:
On Fri, Apr 18, 2014 at 02:02:37PM +0200, Andrzej Hajda wrote:
Separation of the interfaces exposed by the device from
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5250-snow.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
Based on for-next branch of Kgene's linux-samsung tree, with
following patch series:
[PATCH 0/9] Enable USB 3.0 support on Exynos5 systems
https://lkml.org/lkml/2014/4/23/389
These are device tree patches corresponding to the usb driver patch-series:
[PATCH 1/3] usb: ohci-exynos: Make provision
On 04/23/14 19:18, Rafael J. Wysocki wrote:
On Wednesday, April 23, 2014 02:55:50 PM Chander Kashyap wrote:
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.
Tested on
Lee,
On Wed, Apr 23, 2014 at 4:51 AM, Lee Jones lee.jo...@linaro.org wrote:
The tps65090 regulator allows you to specify how long you want it to
wait before detecting an overcurrent condition. Allow specifying that
through the device tree (or through platform data).
Signed-off-by: Doug
An issue was discovered with tps65090 where sometimes the FETs
wouldn't actually turn on when requested (they would report
overcurrent). The most problematic FET was the one used for the LCD
backlight on the Samsung ARM Chromebook (FET1). Problems were
especially prevalent when the device was
On the ARM Chromebook tps65090 has two masters: the AP (the main
processor running linux) and the EC (the embedded controller). The AP
is allowed to mess with FETs but the EC is in charge of charge control.
The tps65090 interupt line is routed to both the AP and the EC, which
can cause quite a
Lee,
On Wed, Apr 23, 2014 at 3:55 AM, Lee Jones lee.jo...@linaro.org wrote:
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
Lee, I don't mind if I apply this and send a pull request
[added Nico in CC]
On Wed, Apr 23, 2014 at 10:25:54AM +0100, Chander Kashyap wrote:
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels
of page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the following issue.
It is a restriction that kernel logical
On 04/23/2014 06:32 AM, Lee Jones wrote:
On Tue, 22 Apr 2014, Doug Anderson wrote:
This series adds the most critical cros_ec changes for newer boards
using cros_ec. Specifically:
* Fixes timing/locking issues with the previously upstreamed (but
never used upstream) cros_ec_spi driver.
On Wed, Apr 23, 2014 at 10:25:52AM +0100, Chander Kashyap wrote:
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by:
Seungwon / Ulf,
On Wed, Apr 23, 2014 at 1:17 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 23 April 2014 01:51, Doug Anderson diand...@chromium.org wrote:
Data errors are completely expected during tuning. Printing them out
is confusing people looking at the kernel logs. They see things
On Wed, Apr 23, 2014 at 05:04:46PM +0200, Andrzej Hajda wrote:
On 04/22/2014 01:51 PM, Russell King - ARM Linux wrote:
Yes, I know that you're desperate to play that down, but you can't get
Not true. I only try to find the best solution and the approach with
multiple re-probing just to
Up till now there was no single generic method to bind devices to their
power domains using Device Tree. Each platform has been doing this using
its own way, example of which are Exynos power domain bindings [1] and
look-up code [2].
This series is intended to change this and provide generic DT
On a number of platforms, devices are part of controllable power
domains, which need to be enabled before such devices can be accessed
and may be powered down when the device is idle to save some power.
This means that on systems that support power domain control using
generic power domains
This patch introduces generic code to perform power domain look-up using
device tree and automatically bind devices to their power domains.
Generic device tree binding is introduced to specify power domains of
devices in their device tree nodes.
Backwards compatibility with legacy
This patch moves Exynos power domain code to use the new generic power
domain look-up framework introduced by previous patch, allowing the new
code to be compiled with CONFIG_ARCH_EXYNOS selected as well.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
.../bindings/arm/exynos/power_domain.txt
On Wed, Apr 23, 2014 at 05:43:28PM +0100, Russell King - ARM Linux wrote:
So, maybe you would like to finally address *my* point about TDA998x
and your solution in a way that provides a satisfactory answer. *Show*
how it can be done, or *outline* how it can be done.
Let me be absolutely clear
Rob,
On Tue, Apr 22, 2014 at 5:04 PM, Rob Clark robdcl...@gmail.com wrote:
So what about, rather than adding drm_panel support to each bridge
individually, we introduce a drm_panel_bridge (with a form of
chaining).. ie:
struct drm_panel_bridge {
struct drm_bridge base;
struct
Sorry for the previous reply,
Here goes the full explaination:
Rob,
On Tue, Apr 22, 2014 at 5:04 PM, Rob Clark robdcl...@gmail.com wrote:
So what about, rather than adding drm_panel support to each bridge
individually, we introduce a drm_panel_bridge (with a form of
chaining).. ie:
Daniel,
On Wed, Apr 23, 2014 at 12:59 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 22, 2014 at 08:06:19PM +0530, Ajay kumar wrote:
Hi Thierry,
On Tue, Apr 22, 2014 at 1:49 PM, Thierry Reding thierry.red...@gmail.com
wrote:
On Tue, Apr 22, 2014 at 04:09:11AM +0530, Ajay Kumar
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.
This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.
The
Describe the clock controller of s3c2410, s3c2440 and s3c2442.
Signed-off-by: Heiko Stuebner he...@sntech.de
Acked-by: Tomasz Figa t.f...@samsung.com
---
.../bindings/clock/samsung,s3c2410-clock.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644
This driver can handle the clock controllers of the socs mentioned above,
as they share a common clock tree with only small differences.
The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure.
As
This adds the necessary init functions to init the clocks from the common
clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy
clock code.
This also includes empty stubs for the *_setup_clocks functions that are
called from the cpufreq driver on resume.
Signed-off-by:
Convert all machines using these cpus to use the ccf clock driver
instead of the legacy Samsung clock implementation.
Some of the more esotheric machines will probably need a fixup, as they
do strange things to the clkout outputs, that I did not really understand
nor have the hardware to check.
Convert the machines using the s3c2410 to use the new driver based
on the common clock framework instead of the legacy Samsung clock driver.
As with the s3c244x, machines using the clkout output will need a fixup
from someone with the hardware.
Signed-off-by: Heiko Stuebner he...@sntech.de
With the move to the common clock framework completed for s3c2410, s3c2440
and s3c2442, the legacy clock code for these machines can go away too.
This also includes the legacy dclk code, as all legacy users are converted.
Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa
Add platform device and select the correct implementation automatically
depending on wether the old samsung_clock or the common clock framework
is enabled.
This is only done for machines already using the old dclk implementation,
as everybody else should move to use dt anyway.
The
Convert the machines using the s3c2410 to use the new driver based
on the common clock framework instead of the legacy Samsung clock driver.
As with the s3c244x, machines using the clkout output will need a fixup
from someone with the hardware.
Signed-off-by: Heiko Stuebner he...@sntech.de
With the move to the common clock framework completed for s3c2410, s3c2440
and s3c2442, the legacy clock code for these machines can go away too.
This also includes the legacy dclk code, as all legacy users are converted.
Signed-off-by: Heiko Stuebner he...@sntech.de
Reviewed-by: Tomasz Figa
Hello.
On 04/23/2014 11:34 PM, Heiko Stübner wrote:
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.
Change this to use a regular clk_set_rate call when using the common
clock framework and
Hi,
On 23.04.2014 22:42, Sergei Shtylyov wrote:
Hello.
On 04/23/2014 11:34 PM, Heiko Stübner wrote:
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.
Change this to use a regular
On 04/24/2014 12:42 AM, Sergei Shtylyov wrote:
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.
Change this to use a regular clk_set_rate call when using the common
clock framework and only
Am Mittwoch, 23. April 2014, 22:55:51 schrieb Tomasz Figa:
Hi,
On 23.04.2014 22:42, Sergei Shtylyov wrote:
Hello.
On 04/23/2014 11:34 PM, Heiko Stübner wrote:
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table
The s3c24xx cpufreq driver needs to change the mpll speed and was doing
this by writing raw values from a translation table into the MPLLCON
register.
Change this to use a regular clk_set_rate call when using the common
clock framework and only write the raw value in the samsung_clock case.
The
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators'
On Thursday, April 24, 2014 9:18 AM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator
Hi,
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches
Hi Andrzej,
Thank you for the comments.
On 04/23/2014 04:37 PM, Andrzej Hajda wrote:
On 04/23/2014 05:45 AM, YoungJun Cho wrote:
Hi again Andrzej,
On 04/23/2014 10:01 AM, YoungJun Cho wrote:
Hi Andrzej
Thank you for comments.
On 04/22/2014 09:15 PM, Andrzej Hajda wrote:
Hi YoungJun,
On
Hi Andrzej,
Thank you for comments.
On 04/23/2014 05:29 PM, Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in
1 - 100 of 107 matches
Mail list logo
