This event indicates that the video device has encountered
a source parameter change during runtime. This can typically be a
resolution change detected by a video decoder OR a format change
detected by an HDMI connector.
This needs to be nofified to the userspace and the application may
be
Hi Kishon,
On Mon, May 12, 2014 at 6:33 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi Gautam,
On Friday 09 May 2014 07:27 PM, Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3
Hi,
On Tuesday 13 May 2014 11:37 AM, Vivek Gautam wrote:
Hi Kishon,
On Mon, May 12, 2014 at 6:33 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi Gautam,
On Friday 09 May 2014 07:27 PM, Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver
On Mon, May 12, 2014 at 10:02 PM, Seungwon Jeon tgih@samsung.com wrote:
As I mentioned in previous version, you put all reset stuff in existing
fifo_reset function.
Although databook mentions ciu_reset case for SBE error, it's not obvious
when ciu_reset is needed in other error cases.
On Tue, May 13, 2014 at 12:13 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Tuesday 13 May 2014 11:37 AM, Vivek Gautam wrote:
Hi Kishon,
On Mon, May 12, 2014 at 6:33 PM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Gautam,
On Friday 09 May 2014 07:27 PM, Vivek Gautam wrote:
On 05/13/14 07:59, Arun Kumar K wrote:
From: Pawel Osciak posc...@chromium.org
When a resolution change point is reached, queue an event to signal the
userspace that a new set of buffers is required before decoding can
continue.
Signed-off-by: Pawel Osciak posc...@chromium.org
Hi Arun,
I've got some more comments w.r.t. the documentation:
On 05/13/14 07:59, Arun Kumar K wrote:
This event indicates that the video device has encountered
a source parameter change during runtime. This can typically be a
resolution change detected by a video decoder OR a format change
On Fri, May 09, 2014 at 08:23:01PM +0530, Ajay Kumar wrote:
implement basic panel controls as a drm_bridge so that
the existing bridges can make use of it.
The driver assumes that it is the last entity in the bridge chain.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
On Monday 12 May 2014 18:38:41 Sonny Rao wrote:
+#ifndef CONFIG_MMC_DW_IDMAC
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
+#endif
Can you change the above like this?
if (IS_ENABLED(CONFIG_MMC_DW_IDMAC) host-use_dma)
flags |=
G2D power domain also controls the CMU block of G2D.
Since clock registers can be accessed anytime for viewing
clk_summary, it can cause a system crash if g2d power domain
is disabled.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
Please also refer to the existing discussion on removal of
On Tuesday 13 May 2014 13:37:33 Kukjin Kim wrote:
Arnd Bergmann wrote:
On Tuesday 22 April 2014, Olof Johansson wrote:
I don't think there's a point in keeping this around. A
single-platform config is just enabling a single platform in the
config, it's not a specific option. I don't
Hi,
From: Arun Kumar K [mailto:arunkk.sams...@gmail.com] On Behalf Of Arun
Kumar K
Sent: Tuesday, March 11, 2014 10:16 AM
From: avnd kiran avnd.ki...@samsung.com
Latest MFC v6 firmware requires tile mode and loop filter setting to be
done as part of Init buffer command, in sync with v7.
Hi Kamil,
On Tue, May 13, 2014 at 2:49 PM, Kamil Debski k.deb...@samsung.com wrote:
Hi,
From: Arun Kumar K [mailto:arunkk.sams...@gmail.com] On Behalf Of Arun
Kumar K
Sent: Tuesday, March 11, 2014 10:16 AM
From: avnd kiran avnd.ki...@samsung.com
Latest MFC v6 firmware requires tile mode
Adding support to enable/disable VBUS controlled by a
regulator, to enable vbus supply on the port.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/phy/phy-exynos5-usbdrd.c | 32
1 file changed, 32 insertions(+)
diff --git
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Also, created a new header file in linux/mfd/syscon/ for
Exynos5 SoCs and put the required PMU offset definitions
Based on 'next' branch of Kishon's phy tree (linux-phy).
Changes from v8:
- Moved out the bindings documentation for the PHY in a separate patch
to avoid checkpatch warnings.
Changes from v7:
- Providing an **alternative** approach for pmu-offset;
instead of getting it from DT, using
Add necessary binding documentation for USB 3.0 DRD PHY present on
Exynos5 SoC series.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 47
1 file changed, 47 insertions(+)
diff --git
in my tree, please let me know.
It seems this one just hit linux-next (in next-20140513) as ARM:
EXYNOS: Map SYSRAM through generic DT bindings. Its commit now contains
this hunk:
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -843,6 +843,7 @@ config ARCH_EXYNOS
select
Hi Kukjin,
On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim kgene@samsung.com wrote:
Abhilash Kesavan wrote:
+ Jonghwan Choi, Seungkon Hwang
From: Leela Krishna Amudala leela.kris...@linaro.org
Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know
Hi Kukjin,
On Tue, May 13, 2014 at 7:58 AM, Kukjin Kim kgene@samsung.com wrote:
Abhilash Kesavan wrote:
From: Leela Krishna Amudala leela.kris...@linaro.org
Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu.
Signed-off-by: Leela Krishna
Hi Bartlomiej,
[...]
- regmap_write(pmu_regmap, S5P_PAD_RET_MAUDIO_OPTION, (1 28));
- regmap_write(pmu_regmap, S5P_PAD_RET_GPIO_OPTION, (1 28));
- regmap_write(pmu_regmap, S5P_PAD_RET_UART_OPTION, (1 28));
- regmap_write(pmu_regmap, S5P_PAD_RET_MMCA_OPTION, (1 28));
-
Hi Pankaj,
[...]
+#define EXYNOS5420_VA_CPU_STATE (S5P_VA_SYSRAM + 0x28)
+#define EXYNOS5420_VA_CPU_ADDR (S5P_VA_SYSRAM_NS + 0x1C)
+
It will be good if we can rebase this change on top of Sachin's SYSRAM
patches [1]
[1]: http://www.spinics.net/lists/arm-kernel/msg329188.html
This is
Hi Alim,
[...]
+ /* Time taken to stabilized XXTI clock */
+ regmap_write(pmu_context-pmu_regmap, EXYNOS5_XXTI_DURATION3,
0x005dc);
+
There is no good reason why XXTI_DURATION3 need to be set here. This
is something that iROM sets, please remove this.
Will remove.
Regards,
Hi Pankaj,
[...]
#include exynos-pmu.h
#include regs-pmu.h
+#include common.h
I think it will be better if we move EXYNOS5420_USE_STANDBY_WFI_ALL
macro into regs-pmu.h itself. It will help us removing dependency of
common.h
from pmu.c, so that in future we can easily move this file
Hi,
On 12/05/14 22:44, Sonny Rao wrote:
Doug mentioned that James Hogan might have an answer. James, are
there Imgtec SoCs which use dw_mmc and use DMA but don't use the
IDMAC? If so, we can add that support into this reset procedure
patch.
Yes, the Toumaz TZ1090 SoC has the dw_mmc
Hi Hans,
On Tue, May 13, 2014 at 1:29 PM, Hans Verkuil hverk...@xs4all.nl wrote:
On 05/13/14 07:59, Arun Kumar K wrote:
From: Pawel Osciak posc...@chromium.org
When a resolution change point is reached, queue an event to signal the
userspace that a new set of buffers is required before
Hi Hans,
Will make the changes you suggested.
Thanks regards
Arun
On Tue, May 13, 2014 at 1:30 PM, Hans Verkuil hverk...@xs4all.nl wrote:
Hi Arun,
I've got some more comments w.r.t. the documentation:
On 05/13/14 07:59, Arun Kumar K wrote:
This event indicates that the video device has
On Tuesday, May 13, Sonny Rao wrote:
On Mon, May 12, 2014 at 10:02 PM, Seungwon Jeon tgih@samsung.com wrote:
As I mentioned in previous version, you put all reset stuff in existing
fifo_reset function.
Although databook mentions ciu_reset case for SBE error, it's not obvious
when
On 05/12/2014 02:45 PM, Rob Clark wrote:
On Mon, May 12, 2014 at 3:06 AM, Andrzej Hajda a.ha...@samsung.com wrote:
On 05/09/2014 05:05 PM, Ajay kumar wrote:
On Fri, May 9, 2014 at 7:29 PM, Rob Clark robdcl...@gmail.com wrote:
On Fri, May 9, 2014 at 5:08 AM, Andrzej Hajda a.ha...@samsung.com
Gentle PING
On 7 May 2014 21:03, Tomasz Figa t.f...@samsung.com wrote:
[CCing more DT-folks :)]
On 07.05.2014 16:19, Rahul Sharma wrote:
On 7 May 2014 19:06, Tomasz Stanislawski t.stanisl...@samsung.com wrote:
On 05/07/2014 12:38 PM, Rahul Sharma wrote:
On 5 May 2014 15:14, Kishon Vijay
Hi Kamil,
On 05/13/14 16:02, Kamil Debski wrote:
Hi,
One small comment below,
-Original Message-
From: Arun Kumar K [mailto:arunkk.sams...@gmail.com] On Behalf Of Arun
Kumar K
Sent: Wednesday, April 23, 2014 2:58 PM
To: linux-me...@vger.kernel.org;
Hi Sachin,
Thank you for the review.
Will address your comments and post updated version.
Regards
Arun
On Thu, May 8, 2014 at 3:09 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
Hi Arun,
Just 2 small nits.
On 7 May 2014 17:00, Arun Kumar K arun...@samsung.com wrote:
MFCv6 encoder needs
Hi Lorenzo
On 9 May 2014 21:02, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
On Mon, May 05, 2014 at 10:27:20AM +0100, Chander Kashyap wrote:
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
On Mon, May 12, 2014 at 11:31:05AM +0900, Jingoo Han wrote:
On Friday, May 09, 2014 8:36 PM, Arnd Bergmann wrote:
As we are preparing to enable multiplatform support on EXYNOS,
we can no longer include mach/*.h or plat/*.h headers from device
drivers.
The s5p-sss driver was just
Hi Tomasz,
On 04/26/2014 09:39 AM, Tomasz Figa wrote:
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa t.f...@samsung.com
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of
This is v6 of the series adding MCPM backend support for SMP secondary boot
and core switching on Samsung's Exynos5420. The patches are based on the mcpm
support added for Exynos5420 in the Chromium kernel repository here:
From: Leela Krishna Amudala leela.kris...@linaro.org
Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu in platsmp and hotplug code.
Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
From: Leela Krishna Amudala leela.kris...@linaro.org
Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know the cpu status.
Signed-off-by: Leela Krishna Amudala leela.kris...@linaro.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
Add generic cluster power control functions for exynos based SoCS
for cluster power up/down and to know the cluster status.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm/mach-exynos/common.h |3 +++
arch/arm/mach-exynos/pm.c | 30 ++
From: Andrew Bresticker abres...@chromium.org
Add device-tree bindings for the ARM CCI-400 on Exynos5420. There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Abhilash Kesavan
Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM
patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch)
merged.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
---
arch/arm/mach-exynos/exynos.c |1
We have an soc check to ensure that the scu and certain A9 specific
registers are not accessed on Exynos5250 (which is A15 based).
Rather than adding another soc specific check for 5420 let us test
for the Cortex A9 primary part number.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
Add machine-dependent MCPM call-backs for Exynos5420. These are used
to power up/down the secondary CPUs during boot, shutdown, s2r and
switching.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Signed-off-by: Inderpal Singh inderpa...@samsung.com
Signed-off-by: Andrew Bresticker
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 25 +
1
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
---
arch/arm/mach-exynos/pm.c | 201 +++
arch/arm/mach-exynos/regs-pmu.h |1 +
2 files changed, 186
On 05/12/2014 06:00 PM, Sean Paul wrote:
On Mon, May 12, 2014 at 3:06 AM, Andrzej Hajda a.ha...@samsung.com wrote:
On 05/09/2014 05:05 PM, Ajay kumar wrote:
On Fri, May 9, 2014 at 7:29 PM, Rob Clark robdcl...@gmail.com wrote:
On Fri, May 9, 2014 at 5:08 AM, Andrzej Hajda a.ha...@samsung.com
This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.
This patchset
From: Tomasz Figa t.f...@samsung.com
This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
dual core and includes following dt nodes:
- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support
The Exynos3250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Signed-off-by: Tomasz Figa t.f...@samsung.com
This patch fix the offset of CPU boot address and don't need to send smc call
of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
WFE in secure mode.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
From: Tomasz Figa t.f...@samsung.com
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual
This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park
On Mon, May 12, 2014 at 3:37 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 12 May 2014 11:44:45 Shaik Ameer Basha wrote:
This is the subset of previous v12 series and includes only the fixes and
enhancements, leaving out the private DT bindings as discussed in the below
thread.
--
On Exynos4212 USE_DELAYED_RESET_ASSERTION must be set in
ARM_CORE1_OPTION register during CPU power down. This is the proper way
of powering down CPU. Additionally without this the CPU clock down won't
work after powering down CPU1 and CPU will work at full frequency chosen
by CPUfreq governor.
Seungwon,
On Mon, May 12, 2014 at 9:52 PM, Seungwon Jeon tgih@samsung.com wrote:
Hi Doug,
On Tue, May 13, 2014, Doug Anderson wrote:
Seungwon,
On Sat, May 10, 2014 at 7:11 AM, Seungwon Jeon tgih@samsung.com wrote:
On Fri, May 09, 2014, Sonny Rao wrote:
On Thu, May 8, 2014 at
Hi Chanwoo,
On 13.05.2014 13:49, Chanwoo Choi wrote:
Hi Tomasz,
On 04/26/2014 09:39 AM, Tomasz Figa wrote:
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa t.f...@samsung.com
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common
On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
[...]
+static int __init exynos_mcpm_init(void)
+{
+ struct device_node *node;
+ int ret = 0;
There is no point in initializing it to 0.
+
+ node = of_find_compatible_node(NULL, NULL, samsung,exynos5420);
On Tue, May 13, 2014 at 1:35 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Fri, May 09, 2014 at 08:23:01PM +0530, Ajay Kumar wrote:
implement basic panel controls as a drm_bridge so that
the existing bridges can make use of it.
The driver assumes that it is the last entity in the
On Tue, May 13, 2014 at 12:43:31PM +0100, Chander Kashyap wrote:
[...]
+static void exynos_suspend(u64 residency)
+{
+ unsigned int mpidr, cpunr;
+
+ mpidr = read_cpuid_mpidr();
+ cpunr = exynos_pmu_cpunr(mpidr);
If I were to be picky, I would compute these values
On Mon, May 12, 2014 at 11:44:45AM +0530, Shaik Ameer Basha wrote:
Cho KyongHo (18):
iommu/exynos: fix build errors
iommu/exynos: change error handling when page table update is failed
iommu/exynos: allocate lv2 page table from own slab
iommu/exynos: fix L2TLB invalidation
On Tue, 13 May 2014, Abhilash Kesavan wrote:
This is v6 of the series adding MCPM backend support for SMP secondary boot
and core switching on Samsung's Exynos5420. The patches are based on the mcpm
support added for Exynos5420 in the Chromium kernel repository here:
On Tue, May 13, 2014 at 2:15 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 13 May 2014 13:37:33 Kukjin Kim wrote:
Arnd Bergmann wrote:
On Tuesday 22 April 2014, Olof Johansson wrote:
I don't think there's a point in keeping this around. A
single-platform config is just enabling a
On Mon, May 5, 2014 at 7:03 PM, Nishanth Menon n...@ti.com wrote:
CPUFreq usage of OPP should be independent of the ordering of type of
data storage inside OPP layer. The current operations can equally be
performed by generic operations.
[RFC]: https://patchwork.kernel.org/patch/4100811/
Changes since v2:
- Reworked based on the PM / OPP: move cpufreq specific helpers out of OPP
layer
patch series posted by Nishanth Menon n...@ti.com.
Changes since v1:
- Boost mode frequencies are specfied as a set of frequencies instead of
specifying them as OPPs. Thanks to Nishanth, Lukasz
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost frequencies from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc:
From: Thomas Abraham thomas...@samsung.com
Add a new optional boost-frequency binding for specifying the frequencies
usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark
Changes since v3:
- Addressed comments from Tomasz Figa t.f...@samsung.com
[http://www.spinics.net/lists/cpufreq/msg09290.html]
- Rebased to v3.15-rc4
Changes since v2:
- Safe operating voltage is not required while switching APLL frequency
since the temporary parent's clock is divided down
From: Thomas Abraham thomas...@samsung.com
Access to samsung clock lock is required to support newer samsung specific
clock types. So change the scope of the samsung clock lock to global. And
prefix 'samsung_clk_' to the existing name of the lock to prevent name space
pollution.
Cc: Tomasz Figa
From: Thomas Abraham thomas...@samsung.com
Lookup for the optional boost-frequency property in cpu0 node and if
available, enable support for boost mode frequencies. The frequencies
usable in boost mode are determined while preparing the cpufreq table
from the list of operating points available.
From; Thomas Abraham thomas...@samsung.com
The clock blocks within the CMU_CPU clock domain are put together into a
new composite clock type called the cpu clock. This clock type requires
configuration data that will be atomically programmed in the multiple
clock blocks encapsulated within the
From: Thomas Abraham thomas...@samsung.com
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new
From: Thomas Abraham thomas...@samsung.com
For all Exynos based platforms, add CPU nodes, operating points and cpu
clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq-cpu0 driver.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham
From: Thomas Abraham thomas...@samsung.com
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type and the independent
clock blocks that made up the arm clock can be removed.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for Exynos specific cpufreq
driver and add the platform device for cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/exynos.c |4 +++-
1 files changed, 3
From: Thomas Abraham thomas...@samsung.com
Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over
to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos
specific cpufreq drivers for these platforms can be removed.
Signed-off-by: Thomas Abraham thomas...@samsung.com
On Tue, May 13, 2014 at 8:03 PM, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Add a new optional boost-frequency binding for specifying the frequencies
usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Hi Lorenzo,
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
[...]
+static int __init exynos_mcpm_init(void)
+{
+ struct device_node *node;
+ int ret = 0;
There is no point
From: Rahul Sharma rahul.sha...@samsung.com
Enable hdmi for exynos5420 based peach-pit board.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 19 +++
arch/arm/boot/dts/exynos5420-pinctrl.dtsi |7 +++
From: Rahul Sharma rahul.sha...@samsung.com
Replace compatible string for HDMI node in Exynos5420. Since
latest restructring in Drm hdmi driver, it is agreed to use
a seperate compatible string for Exynos5420 HDMI IP siince it
uses APB mapped Phy.
Signed-off-by: Rahul Sharma
From: Rahul Sharma rahul.sha...@samsung.com
Enable support for HDMI for exynos5250 based Snow board.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 +-
arch/arm/boot/dts/exynos5250-pinctrl.dtsi |7 +++
From: Rahul Sharma rahul.sha...@samsung.com
Enable hdmi for peach-pi board.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
From: Rahul Sharma rahul.sha...@samsung.com
Enable hdmi for exynos5250 based snow board, exynos5420
based peach pit board and 5800 based peach-pi board.
V4:
1) Removed hdmi_hpd_irq pin from peach-pi board as it already
present in exynos5420-pinctrl.dtsi.
V3:
1) Re-spin on dependent patches.
2)
From: Rahul Sharma rahul.sha...@samsung.com
gpx3-7 is chip specific pin in Exynos5420 for hdmi
hotplug. This pin is moved to exynos5420-pinctrl.dts
and removed from the board file.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts |9
Hi Lorenzo,
On 13 May 2014 22:44, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
On Tue, May 13, 2014 at 12:43:31PM +0100, Chander Kashyap wrote:
[...]
+static void exynos_suspend(u64 residency)
+{
+ unsigned int mpidr, cpunr;
+
+ mpidr = read_cpuid_mpidr();
+
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
Hi Lorenzo,
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
[...]
+static int __init exynos_mcpm_init(void)
+{
Hi Chander,
On Wed, May 14, 2014 at 8:24 AM, Chander Kashyap
chander.kash...@linaro.org wrote:
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
Hi Lorenzo,
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Tue, May 13, 2014 at
On Wed, 14 May 2014, Chander Kashyap wrote:
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
Hi Lorenzo,
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On Tue, May 13, 2014 at 12:58:44PM +0100, Abhilash Kesavan wrote:
in patch 2/2 as well.
Done. If any problems in my tree, please let me know.
It seems this one just hit linux-next (in next-20140513) as ARM:
EXYNOS: Map SYSRAM through generic DT bindings. Its commit now contains
this hunk:
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -843,6
On 14 May 2014 08:32, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Wed, 14 May 2014, Chander Kashyap wrote:
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
Hi Lorenzo,
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
On
Adding missing pm ops so that audio playback works across
suspend and resume cycle.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
sound/soc/samsung/snow.c |1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/samsung/snow.c b/sound/soc/samsung/snow.c
index 0fa89a4..014c177
On Wed, 14 May 2014, Chander Kashyap wrote:
On 14 May 2014 08:32, Nicolas Pitre nicolas.pi...@linaro.org wrote:
On Wed, 14 May 2014, Chander Kashyap wrote:
On 14 May 2014 08:14, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
On Tue, May 13, 2014 at 10:18 PM, Lorenzo Pieralisi
On 14 May 2014 06:32, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost frequencies from device tree and
On 14 May 2014 06:41, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Lookup for the optional boost-frequency property in cpu0 node and if
available, enable support for boost mode frequencies. The frequencies
usable in boost mode are determined while
On 14 May 2014 06:41, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Access to samsung clock lock is required to support newer samsung specific
clock types. So change the scope of the samsung clock lock to global. And
Maybe bit more detail on why exactly
On 14 May 2014 06:41, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched over
to use cpufreq-cpu0 driver for cpufreq functionality. So the Exynos
specific cpufreq drivers for these platforms
On Tue, May 13, 2014 at 10:40 PM, Viresh Kumar viresh.ku...@linaro.org wrote:
On 14 May 2014 06:32, Thomas Abraham ta.oma...@gmail.com wrote:
[...]
+#ifdef CONFIG_CPU_FREQ_BOOST_SW
+ if (of_find_property(dev-of_node, boost-frequency, len)) {
Does this mean another block inside the cpu
to update documentation in patch 2/2 as well.
Done. If any problems in my tree, please let me know.
It seems this one just hit linux-next (in next-20140513) as ARM:
EXYNOS: Map SYSRAM through generic DT bindings. Its commit now contains
this hunk:
--- a/arch/arm/Kconfig
Hi Nicolas,
On Tue, May 13, 2014 at 11:25 PM, Nicolas Pitre
nicolas.pi...@linaro.org wrote:
On Tue, 13 May 2014, Abhilash Kesavan wrote:
This is v6 of the series adding MCPM backend support for SMP secondary boot
and core switching on Samsung's Exynos5420. The patches are based on the mcpm
Olof Johansson wrote:
On Tue, May 13, 2014 at 2:15 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 13 May 2014 13:37:33 Kukjin Kim wrote:
Arnd Bergmann wrote:
On Tuesday 22 April 2014, Olof Johansson wrote:
I don't think there's a point in keeping this around. A
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