Add Murata Manufacturing Co., Ltd. to the list of device tree
vendor prefixes.
Murata manufactures NTC (Negative Temperature Coefficient) based
Thermistors for small scale applications like Mobiles and PDAs.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Mark Rutland
Exynos5420 based Peach PIT board has 4 NTC thermistors to measure
temperatures at various points on the board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the HWMON interface.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Doug Anderson
As Murata Manufactures the NTC based thermistors. The vendor
name in the compatibility is preposed to change to murata
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Chanwoo Choi
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses NTC as the vendor name.
This patch corrects the vendor name also updates the
compatibility strings according to the vendor-prefix.txt
Note: Drivers continue
On 06/25/2014 03:29 PM, Naveen Krishna Chatradhi wrote:
As Murata Manufactures the NTC based thermistors. The vendor
name in the compatibility is preposed to change to murata
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna
Hello Naveen,
On Wed, Jun 25, 2014 at 7:04 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Doug,
On 25 June 2014 03:24, Doug Anderson diand...@chromium.org wrote:
Naveen,
On Tue, Jun 24, 2014 at 5:19 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Exynos5420 based Peach
On sob, 2014-06-14 at 00:43 +0200, Daniel Lezcano wrote:
On 06/11/2014 10:50 AM, Krzysztof Kozlowski wrote:
(...)
Hi,
Shouldn't the exynos_idle_barrier be initialized here?
As it is a static data it will be initialized to zero.
I know you sent the patch almost 2 months ago but I
On Tue, Jun 24, 2014 at 4:35 PM, Kamil Debski k.deb...@samsung.com wrote:
By reboot I guess that you mean typing reboot or by using SysRq magic
and not power cycling?
If so, I had experienced the same symptoms. I guess that the Ethernet
chip is not reset properly and fails to enumerate
Hi,
On Tue, Jun 24, 2014 at 5:08 PM, Tomasz Figa t.f...@samsung.com wrote:
Tested on Odroid U3, with HSIC/USB hub using CLKOUT as reference clock,
with some additional patches.
for all the patches:
Tested-by: Daniel Drake dr...@endlessm.com
Tested on ODROID-U2 alongside
phy:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
We do describe the masked StreamID (SID) but we need to specify the mask
that the SMMU should apply to the
On Tue, Jun 24, 2014 at 10:35:54PM +0100, Olav Haugan wrote:
On 6/24/2014 11:11 AM, Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
On 6/24/2014 2:18 AM, Will Deacon wrote:
On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
We have multiple-master
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
We do describe the masked StreamID (SID) but we need to
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan
On Wednesday 25 June 2014 10:38:25 Will Deacon wrote:
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:17:02 Will Deacon wrote:
On Tue, Jun 24, 2014 at 07:20:56PM +0100, Arnd Bergmann wrote:
On Tuesday 24 June 2014 19:11:50 Will Deacon wrote:
This patch updates hs-200 device tree property from
caps2-mmc-hs200-1.8v to mmc-hs200-1.8v for peach-pit
and peach-pi boards.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5420-peach-pit.dts |2 +-
arch/arm/boot/dts/exynos5800-peach-pi.dts |2 +-
2
On Wed, Jun 25, 2014 at 10:48:31AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:38:25 Will Deacon wrote:
On Wed, Jun 25, 2014 at 10:27:50AM +0100, Arnd Bergmann wrote:
I think the situation is a bit different here: It's less about the corner
cases for the SMMU, but about the
Hi Tomasz,
On Tue, Jun 24, 2014 at 2:57 PM, Tomasz Figa t.f...@samsung.com wrote:
ISP special clocks have dedicated gating registers and so MUX SRC_MASK
register should not be used. This patch fixes the problem of
Exynos4x12-based boards freezing on system suspend, because those
mux outputs
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
From: Doug Anderson diand...@chromium.org
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup source.
Signed-off-by: Doug Anderson diand...@chromium.org
---
All Exynos5 platforms have HSI2C controllers and are needed by
various IPs connected to the boards based on these SoCs. Thus
select this by default for Exynos5 platforms.
Signed-off-by: Sachin Kamat sachin.ka...@samsung.com
Cc: Doug Anderson diand...@chromium.org
---
drivers/i2c/busses/Kconfig |
Hi Tomasz,
On Tue, Jun 24, 2014 at 2:57 PM, Tomasz Figa t.f...@samsung.com wrote:
Due to recently merged patches and previous merge conflicts, the Samsung
PM Debug functionality no longer can be enabled. This patch fixes
incorrect dependency of SAMSUNG_PM_DEBUG on an integer symbol and adds
On Wednesday 25 June 2014 10:57:36 Will Deacon wrote:
So far, I've been avoiding the hardcoding. However, you could potentially
build a system with a small number of SMRs (compared to the number of
StreamIDs) and allocate the StreamIDs in such a way that I think the dynamic
configuration would
On Wed, Jun 25, 2014 at 11:12:13AM +0100, Arnd Bergmann wrote:
On Wednesday 25 June 2014 10:57:36 Will Deacon wrote:
So far, I've been avoiding the hardcoding. However, you could potentially
build a system with a small number of SMRs (compared to the number of
StreamIDs) and allocate the
Kevin Hilman wrote:
Abhilash Kesavan a.kesa...@samsung.com writes:
Hi,
Turning off a cluster when all 4 cores of the cluster are powered off
saves power significantly. Powering off the A15 L2 alone gives around
100mW in savings. Add support for powering off the A15/A7 clusters on
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be to be shared between the
clk-max77686 clock driver and DeviceTree source files.
Signed-off-by: Javier Martinez Canillas
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the #clock-cells property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that
Sachin Kamat wrote:
All Exynos5 platforms have HSI2C controllers and are needed by
various IPs connected to the boards based on these SoCs. Thus
select this by default for Exynos5 platforms.
Yeah right, even upcoming exynos5 SoCs have only HS-I2C not I2C ;-)
Signed-off-by: Sachin Kamat
Yuvaraj Kumar C D wrote:
+ Doug
Hi,
This patch updates hs-200 device tree property from
caps2-mmc-hs200-1.8v to mmc-hs200-1.8v for peach-pit
and peach-pi boards.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Already I've queued same patch into my local but waiting for
Hello Krzysztof,
On 06/25/2014 12:05 PM, Krzysztof Kozlowski wrote:
On czw, 2014-06-19 at 20:20 +0200, Javier Martinez Canillas wrote:
From: Doug Anderson diand...@chromium.org
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup
Hello Naveen,
On Wed, Jun 25, 2014 at 8:29 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses NTC as the vendor name.
This patch corrects the
Tomasz Figa wrote:
Hi Tomasz,
On all Exynos SoCs there is a dedicated CLKOUT pin that allows many of
internal SoC clocks to be output from the SoC. The hardware structure
Yeah, because the CLKOUT pin is used for measure of the clock for debug on all
of exynos SoCs commonly.
of CLKOUT
Hello Naveen,
On Wed, Jun 25, 2014 at 8:29 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Exynos5420 based Peach PIT board has 4 NTC thermistors to measure
temperatures at various points on the board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when
This patch removes an extra read of FIFO_STATUS register in the interrrupt
service routine. Which is read again before the actual use.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c |1 -
1 file changed, 1 deletion(-)
diff --git
This patch removes an extra line and fixes a styling nit
in exynos5_i2c_message_start()
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c
Hello Javier,
On 25 June 2014 16:06, Javier Martinez Canillas jav...@dowhile0.org wrote:
Hello Naveen,
On Wed, Jun 25, 2014 at 8:29 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based
Thanks Inki,
One more thing. mixer_layer_update is only called on for mixer version;
MXR_VER_16_0_33_0, MXR_VER_128_0_0_184. This condition
should have taken care of Exynos4 scenarios. What you say?
Regards,
Rahul Sharma.
On 24 June 2014 20:20, Inki Dae inki@samsung.com wrote:
2014-06-24
On Mon, Jun 23, 2014 at 06:27:04PM +0100, Doug Anderson wrote:
Andreas,
On Sun, Jun 22, 2014 at 6:21 PM, Andreas Färber afaer...@suse.de wrote:
It's vsys-l{1,2}-supply, not vsys_l{1,2}-supply.
Signed-off-by: Andreas Färber afaer...@suse.de
---
On 05/31/2014 12:17 AM, Tomasz Figa wrote:
On 30.05.2014 20:42, Kukjin Kim wrote:
On 05/31/14 03:19, Andreas Färber wrote:
Am 28.05.2014 06:13, schrieb Sachin Kamat:
Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with Exynos4412 being the
Hi Naveen,
On Wed, Jun 25, 2014 at 4:08 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch removes an extra line and fixes a styling nit
in exynos5_i2c_message_start()
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c |
Hi Kukjin,
On 25.06.2014 12:36, Kukjin Kim wrote:
Tomasz Figa wrote:
Hi Tomasz,
On all Exynos SoCs there is a dedicated CLKOUT pin that allows many of
internal SoC clocks to be output from the SoC. The hardware structure
Yeah, because the CLKOUT pin is used for measure of the clock for
Naveen Krishna Chatradhi wrote:
+ Jean Delvare, Guenter Roeck
I'm adding maintainers for drivers/hwmon/ntc* but I'm not sure.
Hi,
This series looks good to me. I will take 3/4 and 4/4 for exynos DT changes once
hwmon/ntc maintainer pick the others.
Thanks,
Kukjin
As Murata is the
Abhilash Kesavan wrote:
Hi Russell and Tomasz,
+Arnd
On Tue, Jun 24, 2014 at 9:41 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Mon, Jun 16, 2014 at 09:37:14AM +0530, Abhilash Kesavan wrote:
Hi Kukjin,
On Fri, May 23, 2014 at 8:31 AM, Abhilash Kesavan
Doug Anderson wrote:
The original code for the exynos i2c controller registered for the
noirq variants. However during review feedback it was moved to
SIMPLE_DEV_PM_OPS without anyone noticing that it meant we were no
longer actually noirq (despite functions named
exynos5_i2c_suspend_noirq
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the
On Wed, Jun 25, 2014 at 10:30:46AM +0530, Abhilash Kesavan wrote:
I see that you have sent a patch out that ensures both part and
implementor number are checked. Currently, my patch has been applied
to the fixes branch of the arm-soc tree and I wanted to know how to
proceed (without it there
Hi Yuvaraj.
This patch looks like similar Jaehoon's.
Is it resending?
Anyway, I added some comments below.
On Wed, June 25, 2014, Jaehoon Chung wrote:
On 06/25/2014 03:00 AM, Doug Anderson wrote:
Yuvaraj,
On Mon, Jun 23, 2014 at 3:45 AM, Yuvaraj Kumar C D yuvaraj...@gmail.com
wrote:
Hi Kukjin,
Please take this fix in your tree.
Regards,
Rahul Sharma
On 19 June 2014 11:35, Sachin Kamat sachin.ka...@samsung.com wrote:
On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by: Rahul
Hi Rahul,
On 25.06.2014 13:22, Rahul Sharma wrote:
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.
Best regards,
Tomasz
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To unsubscribe from this list: send the line unsubscribe
Hi Vasily,
On 23.06.2014 22:29, Vasily Khoruzhick wrote:
There's a several typos in a driver: 2410 instead of S3C2410
and wrong argument to ARRAY_SIZE(). They prevent s3c2410
from properly booting.
Thanks for fixing this. I will apply and send to Mike with other fixes.
Same for patch 2/2.
Tomasz Figa wrote:
Hi Rahul,
On 25.06.2014 13:22, Rahul Sharma wrote:
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.
Yes, I also checked the datasheet and this change is
Doug Anderson wrote:
Mark or Kukjin,
Hi,
On Thu, Jun 12, 2014 at 8:59 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
spi-s3c64xx.c driver expects
1. chip select gpios from cs-gpio(singular) under the
Hi Charles,
On 18.06.2014 11:52, Charles Keepax wrote:
In the move to this clock driver the hookups for the SPI clocks were
dropped, which causes my system Cragganmore (s3c6410 based) to be unable
to locate any spibus clocks. This patch adds them back in.
When taking the clock from the epll
On 10.06.2014 17:39, Tomasz Figa wrote:
Hi,
On 26.05.2014 13:56, Shaik Ameer Basha wrote:
From: Arun Kumar K arun...@samsung.com
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K arun...@samsung.com
Sachin Kamat wrote:
+ Russell
In a multiplatform config, the low level debug option shows several
UART port entries. Improve the user visible string so that it becomes
clear to the user about Samsung UART ports.
While at it also remove some lines from the help text that are no
longer
On 25.06.2014 12:09, Daniel Drake wrote:
Hi Tomasz,
On Tue, Jun 24, 2014 at 2:57 PM, Tomasz Figa t.f...@samsung.com wrote:
Due to recently merged patches and previous merge conflicts, the Samsung
PM Debug functionality no longer can be enabled. This patch fixes
incorrect dependency of
Am 25.06.2014 12:47, schrieb Mark Rutland:
On Mon, Jun 23, 2014 at 06:27:04PM +0100, Doug Anderson wrote:
Andreas,
On Sun, Jun 22, 2014 at 6:21 PM, Andreas Färber afaer...@suse.de wrote:
It's vsys-l{1,2}-supply, not vsys_l{1,2}-supply.
Signed-off-by: Andreas Färber afaer...@suse.de
---
Sachin Kamat wrote:
On Fri, May 30, 2014 at 11:49 PM, Andreas Färber afaer...@suse.de wrote:
Am 28.05.2014 06:13, schrieb Sachin Kamat:
Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with Exynos4412 being the only
exception.
Due to recently merged patches and previous merge conflicts, the Samsung
PM Debug functionality no longer can be enabled. This patch fixes
incorrect dependency of SAMSUNG_PM_DEBUG on an integer symbol and adds
missing header inclusion.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based boards.
This patch fixes the issue by
Am 25.06.2014 13:43, schrieb Kukjin Kim:
Sachin Kamat wrote:
On Fri, May 30, 2014 at 11:49 PM, Andreas Färber afaer...@suse.de wrote:
Am 28.05.2014 06:13, schrieb Sachin Kamat:
Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with
On 2014년 06월 25일 19:42, Rahul Sharma wrote:
Thanks Inki,
One more thing. mixer_layer_update is only called on for mixer version;
MXR_VER_16_0_33_0, MXR_VER_128_0_0_184. This condition
should have taken care of Exynos4 scenarios. What you say?
There was my missing point. :) Already
On 06/25/2014 03:59 AM, Laura Abbott wrote:
On 6/24/2014 10:47 AM, Laura Abbott wrote:
On 6/23/2014 11:32 AM, Kevin Hilman wrote:
On Sun, Jun 22, 2014 at 8:56 PM, Tushar Behera trbli...@gmail.com wrote:
Adding linux-samsung-soc and linux-arm-kernel ML for wider audience.
On 06/19/2014 04:12
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB
On Wed, Jun 25, 2014 at 6:43 AM, Andreas Färber afaer...@suse.de wrote:
Am 25.06.2014 12:47, schrieb Mark Rutland:
On Mon, Jun 23, 2014 at 06:27:04PM +0100, Doug Anderson wrote:
Andreas,
On Sun, Jun 22, 2014 at 6:21 PM, Andreas Färber afaer...@suse.de wrote:
It's vsys-l{1,2}-supply, not
On Wed, Jun 25 2014 at 01:21:17 PM, Rob Herring robherri...@gmail.com wrote:
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have
Facilitate getting required 3.3V and 1.0V VDD supply for
EHCI controller on Exynos.
With the patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for smdk5250,
the exynos systems turn on only minimal number of
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for smdk5250,
the exynos systems turn on only minimal number of
This series is doing code cleanup under arch/arm/mach-exynos.
These patches have been separated from main exynos pmu v4 patch
posted here [1].
[1]: https://lkml.org/lkml/2014/5/10/29
Changes Since v4:
- Rebased on latest for-next of Kukjin Kim's tree.
- Removing file path comment from
As exynos_cpuidle_init and exynos_cpufreq_init function have just one lines
of code for registering platform devices. We can move these lines to
exynos_dt_machine_init and delete exynos_cpuidle_init and exynos_cpufreq_init
function. This will help in reducing lines of code in exynos.c, making it
As machine function ops are used only in this file let's make
them static. Also remove unused and unwanted declarations from
common.h.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/common.h |8
While making PMU implementation to be device tree based, there are
few register offsets related with SYSREG present in regs-pmu.h, so
let's make a new header file regs-sys.h to keep all such SYSREG
related register offsets and remove them from regs-pmu.h
Signed-off-by: Pankaj Dubey
Current pm_domain.c file uses S5P_INT_LOCAL_PWR_EN definition from
regs-pmu.h and hence needs to include this header file. As there is
no other user of S5P_INT_LOCAL_PWR_EN definition other than pm_domain,
to remove regs-pmu.h header file dependency from pm_domain.c it's
better we define this
Many files under arm/mach-exynos are having file path in file
comment section which is invalid now.
So for better code maintainability let's remove them.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/headsmp.S
This patch removes unnecessary header file inclusion from pmu.c.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/pmu.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-exynos/pmu.c
On Wed, Jun 25, 2014 at 08:41:13PM +0900, Kukjin Kim wrote:
Sachin Kamat wrote:
+ Russell
In a multiplatform config, the low level debug option shows several
UART port entries. Improve the user visible string so that it becomes
clear to the user about Samsung UART ports.
While at it
Sure Tomasz, Kukjin.
Thanks for the update.
Regards.
On 25 June 2014 16:56, Kukjin Kim kgene@samsung.com wrote:
Tomasz Figa wrote:
Hi Rahul,
On 25.06.2014 13:22, Rahul Sharma wrote:
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll
On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
From: Doug Anderson diand...@chromium.org
For UHS cards we need the ability to switch voltages from 3.3V to
1.8V. Add support to the dw_mmc driver to handle this. Note that
dw_mmc
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi | 24
1 file changed, 24 insertions(+)
diff
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB
Hello,
This is the second version of the initial patch series adding support
for Exynos 4412 based Odroid X2 and U2/U3/U3+ boards and improving
support for Odroid X.
Complete USB support for Odroid U2/U3/U3+ still requires some fixes in
Exynos4 USB2 Phy driver and clock driver for CLKOUT:
From: Kamil Debski k.deb...@samsung.com
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski k.deb...@samsung.com
[removed incorrect port@2 node]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
From: Kamil Debski k.deb...@samsung.com
On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3
source, which is also connected to LAN9730 chip's nRESET signal. To
reset lan chip on system reboot, the BUCK8 output should not be used in
'always on' mode. This change has no impact on X/X2
This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: Marek Szyprowski
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++
arch/arm/mm/cache-l2x0.c | 46 ++
2 files changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec callback
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set
According to the documentation, TAG_LATENCY_CTRL and DATA_LATENCY_CTRL
registers of L2C-310 can be written only in secure mode, so
l2c_write_sec() should be used to change them, instead of plain
writel_relaxed().
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 16
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.
First four patches extend existing support for secure
For certain platforms (e.g. Exynos) it is necessary to read back some
values from registers before they can be written (i.e. SMC calls that
set multiple registers per call), so base address of L2C controller is
needed for .write_sec operation. This patch adds base argument to
.write_sec callback
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from
On Wed, Jun 25, 2014 at 6:56 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
From: Kamil Debski k.deb...@samsung.com
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski k.deb...@samsung.com
[removed incorrect port@2 node]
This patch series, modifies Exynos Power Management Unit (PMU) related code
for converting it into a platform_driver. This is also preparation for moving
PMU related code out of machine folder into a either drivers/mfd, or
drivers/power or some other suitable place so that ARM64 based SoC can
Add support for mapping Samsung Power Management Unit (PMU)
base address from device tree.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/exynos.c | 45 +
2 files changed, 46
This patch modifies Exynos Power Management Unit (PMU) initialization
implementation in following way:
- Added platform driver support and probe function where Exynos PMU
driver will register itself as syscon provider with syscon framework.
- Added platform struct exynos_pmu_data to hold
Under arm/mach-exynos many files are using PMU register offsets.
Since we have added support for accessing PMU base address via DT,
now we can remove PMU mapping from exynosX_iodesc. Let's convert
all these access using iomapped address.
This will help us in removing static mapping of PMU base
As we have removed static mappings from regs-pmu.h it does not
need map.h anymore. But platsmp.c needed this and till now it
got included indirectly. So lets move header inclusion of
mach/map.h from regs-pmu.h to platsmp.c.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Reviewed-by: Tomasz
On 06/24/2014 11:29 PM, Naveen Krishna Chatradhi wrote:
Add Murata Manufacturing Co., Ltd. to the list of device tree
vendor prefixes.
Murata manufactures NTC (Negative Temperature Coefficient) based
Thermistors for small scale applications like Mobiles and PDAs.
Signed-off-by: Naveen Krishna
On 06/24/2014 11:29 PM, Naveen Krishna Chatradhi wrote:
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses NTC as the vendor name.
This patch corrects the vendor name also updates the
compatibility strings
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