On Fri, Aug 01, 2014 at 06:09:48PM +0100, Mark Brown wrote:
From: Mark Brown broo...@linaro.org
When printing size_t values we should use the %zd or %zx format specifier
in order to ensure the value is displayed correctly and avoid warnings from
sparse.
Applied, thanks
--
~Vinod
--
To
Hi Andreas,
Thanks for the comments.
On Fri, Aug 1, 2014 at 10:24 PM, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 01.08.2014 18:24, schrieb Ajay Kumar:
Add DT nodes for panel-simple auo,b133htn01 panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also add panel
Add DT nodes for panel-simple auo,b133htn01 panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also, add panel phandle needed by dp to enable display on peach_pi.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Remove simple-panel compatible
This series add the model_name, manufacturer and voltage_min_design
files from the power supply monitor class sysfs interface that were
missing for the sbs-battery driver. The commits were taken from the
Chrome OS 3.8 downstream kernel and patches were squashed when they
just fixed bugs introduced
From: Simon Que s...@chromium.org
sbs-battery has a max design voltage but not a min design voltage field.
The SBS spec only has one design voltage:
http://www.sbs-forum.org/specs/sbdat110.pdf
Currently this is being used for max design voltage. This patch uses it
for min design voltage as
From: cychiang cychi...@chromium.org
This CL supports two power_supply_property items for smart battery:
POWER_SUPPLY_PROP_MANUFACTURER and POWER_SUPPLY_PROP_MODEL_NAME such
that battery information 'manufacturer' and 'model_name' can be exported
to sysfs.
Signed-off-by: Cheng-Yi Chiang
On 2014-08-04 02:28, Inki Dae wrote:
Oops, sorry. I didn't check v2.
No problem :)
It would be good if you could also check the libdrm patches that I've
resent some while ago.
With best wishes,
Tobias
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the body
Currently there is no mechanism for validation of the PLL rate tables
in the samsung clock driver. In addition, the implementation does not
allow the use ``heterogenous'' tables (i.e., tables whose entries can
correspond to different clock sources).
For instance, consider the VPLL clock from
This patch series changes the way PLL clocks are registered, mainly to
add validation of rate tables. What follows is a list of changes
introduced by the patch:
- Validation of PLL rate tables
- Added support for heterogenous rate tables.
- Removed explicit dependency on the input clock source
All the structures and tables related to the PLL clock
initialization that were previously as __initdata are now marked
as __initconst.
Signed-off-by: Humberto Silva Naves hsna...@gmail.com
---
drivers/clk/samsung/clk-exynos3250.c | 6 +++---
drivers/clk/samsung/clk-exynos4.c| 16
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based
Hi,
On Monday, August 04, 2014 04:09:51 PM Bartlomiej Zolnierkiewicz wrote:
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based
Andreas,
On Fri, Aug 1, 2014 at 5:52 PM, Andreas Färber afaer...@suse.de wrote:
Adds initial support for the HP Chromebook 11.
Cc: Vincent Palatin vpala...@chromium.org
Cc: Doug Anderson diand...@chromium.org
Cc: Stephan van Schaik step...@synkhronix.com
Signed-off-by: Andreas Färber
Andreas,
On Sat, Aug 2, 2014 at 3:25 AM, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 02.08.2014 06:57, schrieb Doug Anderson:
On Fri, Aug 1, 2014 at 7:34 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 08/02/2014 02:52 AM, Andreas Färber wrote:
Based on the
Hello Doug,
On 08/04/2014 05:22 PM, Doug Anderson wrote:
+
+pinctrl_0 {
+ s5m8767_dvs: s5m8767-dvs {
+ samsung,pins = gpd1-0, gpd1-1, gpd1-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
Hello Doug,
On 08/04/2014 05:42 PM, Doug Anderson wrote:
Both of you mentioned limitations of cros_ec i2c passthrough leading to
a forked tps65090 driver downstream - I don't think I can be of help
there, as I guess simply copying a driver will not be an option. ;)
EXYNOS cpuidle driver is enabled (in both cases the default
exynos_defconfig config is used and CPU1-3 are offlined).
Depends on:
- next-20140804 branch of linux-next kernel tree
- [PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
(http://www.mail-archive.com/linux-samsung-soc
Replace EXYNOS_BOOT_VECTOR_ADDR and EXYNOS_BOOT_VECTOR_FLAG macros
by exynos_boot_vector_addr() and exynos_boot_vector_flag() static
inlines.
This patch shouldn't cause any functionality changes.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park
Register cpuidle platform device on Exynos4x12 SoCs allowing EXYNOS
cpuidle driver usage on these SoCs.
AFTR mode reduces power consumption on Trats2 board (Exynos4412 SoC
with secure firmware enabled) by ~12% when EXYNOS cpuidle driver is
enabled (in both cases the default exynos_defconfig
* Move cp15 registers saving to exynos_save_cp15() helper and add
additional helper usage to do_idle firmware method.
* Use resume firmware method instead of exynos_cpu_restore_register()
and skip exynos_cpu_save_register() on boards with secure firmware
enabled.
* Use sysram_ns_base_addr
Add S5P_CENTRAL_SEQ_OPTION register setup to cpuidle AFTR mode code
by moving the relevant code from exynos_pm_suspend() (used only by
suspend) to exynos_pm_central_suspend() (used by both suspend and
AFTR). Without this setup AFTR mode doesn't show any benefit over
WFI one (at least on
On some platforms (i.e. EXYNOS ones) more than one idle mode is
available and we need to distinguish them in firmware do_idle method.
Add mode parameter to do_idle firmware method and AFTR mode support
to EXYNOS do_idle implementation.
This change is a preparation for adding secure firmware
On Wed, Jun 25, 2014 at 03:32:03PM +0530, Sachin Kamat wrote:
All Exynos5 platforms have HSI2C controllers and are needed by
various IPs connected to the boards based on these SoCs. Thus
select this by default for Exynos5 platforms.
Signed-off-by: Sachin Kamat sachin.ka...@samsung.com
Cc:
This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys Mobile storage host databook.
Signed-off-by: Sonny Rao sonny...@chromium.org
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
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