On Thu, Mar 26, 2015 at 01:43:12PM +0100, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
Implement domain_alloc and domain_free iommu-ops as a
replacement for domain_init/domain_destroy.
Signed-off-by: Joerg Roedel jroe...@suse.de
---
drivers/iommu/tegra-smmu.c | 41
On Thu, Mar 26, 2015 at 01:43:03PM +0100, Joerg Roedel wrote:
Changes v1-v2:
* Rebased to v4.0-rc5
* Converted domain-types to a bit-field
Hi,
here is patch-set to replace the existing domain_init and
domain_destroy iommu-ops with the new domain_alloc and
domain_free
Hello Inki,
On Fri, Mar 27, 2015 at 2:47 AM, Inki Dae inki@samsung.com wrote:
Right, this is not documented but if you have ever checked exynos drm
driver tree, then I think you could know how we use the prefix. Of
course, I don't like to force the use of this prefix but if you and
other
Dear Kukjin,
How would you like to proceed? You did not respond to my email nor to
Bartlomiej's questions.
You questioned the soc_is_exynos(). I replied but there was no
answer from you. My last reply:
2015-03-18 9:57 GMT+01:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
Probably
Prevent possible NULL pointer dereference of pointer returned by
of_find_device_by_node(). Handle this by skipping such power domain.
Additionally fail the init on kstrdup() failure. Such case is actually
not fatal because the name for power domain allocated by kstrdup() is
used only in printk.
Prevent possible NULL pointer dereference if of_iomap() fails. Handle
the error by skipping such power domain.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/pm_domains.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
On Thu, Mar 26, 2015 at 01:43:13PM +0100, Joerg Roedel wrote:
From: Joerg Roedel jroe...@suse.de
Implement domain_alloc and domain_free iommu-ops as a
replacement for domain_init/domain_destroy.
Signed-off-by: Joerg Roedel jroe...@suse.de
---
drivers/iommu/tegra-gart.c | 67
Hi Sjoerd,
When disabling the samsung PWM the output state remains at the level
it was in the end of a pwm cycle. In other words, calling pwm_disable
when at 100% duty will keep the output active, while at all other
setting the output will go/stay inactive. On top of that the samsung
PWM
Prevent possible NULL pointer dereference if of_iomap() fails. Handle
the error by skipping such power domain.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v1:
1. Add missing kfree() of domain name (allocated with kstrdup()).
---
arch/arm/mach-exynos/pm_domains.c
Prevent possible NULL pointer dereference of pointer returned by
of_find_device_by_node(). Handle this by skipping such power domain.
Additionally fail the init on kstrdup() failure. Such case is actually
not fatal because the name for power domain allocated by kstrdup() is
used only in printk.
Add missing of_node_put() to:
1. Error return path if allocating memory for exynos_pm_domain failed.
2. Second iteration over power domains if a child domain was not present
or was incomplete.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Reported-by: Karol Wrona
Hi Tobias,
2015-03-27 Tobias Jakobi tjak...@math.uni-bielefeld.de:
Hello!
Gustavo Padovan wrote:
I would keep calling these two vars x_ratio and y_ratio. I don't see a
reason
to change the name here.
Right, I'm going to change this. Also I was thinking of basing the patch
on your
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system
Hello,
Suspend-to-RAM is currently not working. Abhilash Kesavan traced down
to the MDMA0 DMA controller clock to be disabled during suspend and
that it must stay enaled during suspend or the system is not able to
resume.
This series is an attempt to fix the issue and is composed of patches:
Hello Abhilash,
On 03/27/2015 03:06 PM, Abhilash Kesavan wrote:
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like
2015-03-27 15:21 GMT+01:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
The MDMA0 controller clock needs to be enabled to allow the
system to be resumed when entering into a suspend state.
The clock is disabled as a part of the runtime pm for the
pl330 DMA driver so the system fails to resume. So to allow
the system to grab the clock and make sure that it stays
2015-03-23 11:49 GMT+01:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
This reverts commit 2d2c9a8d0a4f90e298315d2f4a282d8bd5d45e5c
(ARM: dts: add display power domain for exynos5250).
The mentioned commit added a domain definition for the DISP1
power domain and references to it
Hello Krzysztof,
On 03/27/2015 03:29 PM, Krzysztof Kozlowski wrote:
2015-03-23 11:49 GMT+01:00 Javier Martinez Canillas
I looked at the DP and FIMD drivers and with great help of Andrzej
Hajda found the issue: the FIMD driver does not enable DP clock
(DP_MIE_CLKCON register). The process
Hello Javier,
On 27/03/15 15:21, Javier Martinez Canillas wrote:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend
Hello Sylwester,
Thanks a lot for your feedback.
On 03/27/2015 03:36 PM, Sylwester Nawrocki wrote:
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+/*
+ * Exynos5420 requires the MDMA0 controller clock to be
+ *
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested Andrzej Hajda: the DP clock was disabled.
This clock is required by
Commit 42773b28e71d (clk: samsung: exynos4: Enable ARMCLK
down feature) enabled ARMCLK down feature on all Exynos4
SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature
causes a lockup when ondemand cpufreq governor is used.
Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs.
This
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested Andrzej Hajda: the DP clock was disabled.
This clock is required by
Hello Javier,
2015-03-27 20:08 GMT+09:00 Javier Martinez Canillas jav...@dowhile0.org:
Hello Inki,
On Fri, Mar 27, 2015 at 2:47 AM, Inki Dae inki@samsung.com wrote:
Right, this is not documented but if you have ever checked exynos drm
driver tree, then I think you could know how we use
Hello Krzysztof,
Thanks a lot for your feedback.
On 03/27/2015 03:38 PM, Krzysztof Kozlowski wrote:
2015-03-27 15:21 GMT+01:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm
Commit 26ab1c62b6e1 (cpufreq: exynos5250: Set APLL rate
using CCF API) removed the last user of -need_apll_change
method. Remove it and then cleanup exynos_cpufreq_scale()
accordingly.
This patch was tested on Exynos4412 SoC based Trats2 board.
There should be no functional changes caused by
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Hi,
Here goes the full support for atomic modesetting on exynos. I've
split the patches in the various phases of atomic support.
These patches sits on top of the clean up patches I've sent yesterday
to this mailing list[1].
Gustavo
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The new atomic infrastructure needs the .mode_set_nofb() callback to
update CRTC timings before setting any plane.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 60
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that no one is using the functions exported by exynos_drm_plane due
to the atomic conversion we can make remove some of the them or make them
static.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Set CRTC, planes and connectors to use the default implementations from
the atomic helper library. The helpers will work to keep track of state
for each DRM object.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Rip out the check from exynos_update_plane() and create
exynos_check_plane() for the check phase enabling use to use
the atomic helpers to call our check and update phases when updating
planes.
Update all users of exynos_update_plane()
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The atomic helper to disable planes also uses the optional
.atomic_disable() helper. The unique operation it does is calling
.win_disable()
exynos_drm_fb_get_buf_cnt() needs a fb check too to avoid a null pointer.
Signed-off-by: Gustavo
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
PageFlips now use the atomic helper to work through the atomic modesetting
API. Async page flips are not supported yet.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 63
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Use drm_atomic_set_fb_for_plane() in the legacy page_flip path to keep
track of the framebuffer pointer and reference.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 3 +++
1
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete we can switch the update/disable_plane
callbacks to their atomic version.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fb.c| 3 +++
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that phase 1 and 2 are complete switch .set_config helper to
use the atomic one.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1
Hello Krzysztof,
On 03/27/2015 05:08 PM, Krzysztof Kozlowski wrote:
After adding display power domain for Exynos5250 in commit
2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250) the
display on Chromebook Snow and others stopped working after boot.
The reason for this suggested
The MDMA0 controller clock needs to be enabled to allow the
system to be resumed when entering into a suspend state.
The clock is disabled as a part of the runtime pm for the
pl330 DMA driver so the system fails to resume. So to allow
the system to grab the clock and make sure that it stays
Commit ae43b3289186 (ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12) added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this clock needs to remain enabled in order to make
the system
Am Donnerstag, 26. März 2015, 13:43:03 schrieb Joerg Roedel:
Changes v1-v2:
* Rebased to v4.0-rc5
* Converted domain-types to a bit-field
Hi,
here is patch-set to replace the existing domain_init and
domain_destroy iommu-ops with the new domain_alloc and
domain_free
On 27 March 2015 at 22:02, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Commit 26ab1c62b6e1 (cpufreq: exynos5250: Set APLL rate
using CCF API) removed the last user of -need_apll_change
method. Remove it and then cleanup exynos_cpufreq_scale()
accordingly.
This patch was tested
On Thu, 2015-03-26 at 13:43 +0100, Joerg Roedel wrote:
Changes v1-v2:
* Rebased to v4.0-rc5
* Converted domain-types to a bit-field
Hi,
here is patch-set to replace the existing domain_init and
domain_destroy iommu-ops with the new domain_alloc and
domain_free callbacks
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