On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
[ ... ]
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index
0fd5650..f313a7a 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
On Monday, April 28, 2014 10:24 PM, Steve Capper wrote:
On Sun, Apr 27, 2014 at 12:37:35PM +0900, Jungseok Lee wrote:
On Thursday, April 24, 2014 1:02 AM, Steve Capper wrote:
On Fri, Apr 18, 2014 at 04:59:20PM +0900, Jungseok Lee wrote:
[ ... ]
This is overly complicated. For 4
Steve's comment
- introduced Steve's create_pgd_entry
Jungseok Lee (7):
arm64: Use pr_* instead of printk
arm64: Decouple page size from level of translation tables
arm64: Introduce a kernel configuration option for VA_BITS
arm64: Add a description on 48-bit address space with 4KB
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays
or there is about 512GB RAM.
References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
+ 2 levels host
9) 64KB + 2 levels guest on 64KB + 2 levels host
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm/include/asm/kvm_mmu.h
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/Kconfig | 36 +++-
arch/arm64/include/asm/page.h |2 +-
arch/arm64/include/asm/pgalloc.h |4 ++--
arch/arm64/include
On Tuesday, April 29, 2014 11:45 PM, Catalin Marinas wrote:
On Tue, Apr 29, 2014 at 05:59:23AM +0100, Jungseok Lee wrote:
+config ARM64_VA_BITS
+ int Virtual address space size
+ range 39 39 if ARM64_4K_PAGES ARM64_3_LEVELS
+ range 42 42 if ARM64_64K_PAGES ARM64_2_LEVELS
On Wednesday, April 30, 2014 5:35 AM, Mitchel Humpherys wrote:
On Mon, Apr 28 2014 at 09:59:14 PM, Jungseok Lee jays@samsung.com wrote:
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Cc
On Wednesday, April 30, 2014 2:04 AM, Catalin Marinas wrote:
On Tue, Apr 29, 2014 at 05:59:33AM +0100, Jungseok Lee wrote:
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index
0fd5650..03ec424 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
On Tuesday, April 29, 2014 11:41 PM, Catalin Marinas wrote:
Jungseok,
Hi, Catalin
On Tue, Apr 29, 2014 at 05:59:20AM +0100, Jungseok Lee wrote:
+choice
+ prompt Level of translation tables
+ default ARM64_3_LEVELS if ARM64_4K_PAGES
+ default ARM64_2_LEVELS if ARM64_64K_PAGES
On Tuesday, April 29, 2014 11:48 PM, Catalin Marinas wrote:
On Tue, Apr 29, 2014 at 05:59:27AM +0100, Jungseok Lee wrote:
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -8,10 +8,11 @@ This document describes the virtual memory layout
used by the AArch64
On Wednesday, April 30, 2014 10:12 PM, Catalin Marinas wrote:
On Wed, Apr 30, 2014 at 07:41:40AM +0100, Jungseok Lee wrote:
On Tuesday, April 29, 2014 11:48 PM, Catalin Marinas wrote:
On Tue, Apr 29, 2014 at 05:59:27AM +0100, Jungseok Lee wrote:
--- a/Documentation/arm64/memory.txt
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays
This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
://www.spinics.net/linux/lists/arm-kernel/msg319552.html
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/Kconfig | 45
or there is about 512GB RAM.
References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch
size as per Steve's comment
- introduced Steve's create_pgd_entry
Changes since v4:
- hided translation level options from menuconfig as per Catalin's comment
- dropped some printk changes as per Mitchel's comment
- squashed VA_BITS related patches into a single patch
Jungseok Lee (6):
arm64: Use
+ 2 levels host
9) 64KB + 2 levels guest on 64KB + 2 levels host
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Christoffer Dall christoffer.d...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm/include/asm/kvm_mmu.h
On Thursday, May 01, 2014 7:06 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:33:56AM +0900, Jungseok Lee wrote:
This patch adds virtual address space size and a level of translation
tables to kernel configuration. It facilicates introduction of
different MMU options, such as 4KB
On Thursday, May 01, 2014 7:06 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:34:05AM +0900, Jungseok Lee wrote:
This patch adds memory layout and translation lookup information about
48-bit address space with 4K pages. The description is based on 4
levels of translation tables
On Friday, May 02, 2014 8:17 PM, Christoffer Dall wrote:
On Fri, May 02, 2014 at 10:57:09AM +0900, Jungseok Lee wrote:
On Thursday, May 01, 2014 7:06 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:33:56AM +0900, Jungseok Lee wrote:
[...]
+
+choice
+ prompt
On Tuesday, May 06, 2014 7:49 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:34:16AM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due
On Tuesday, May 06, 2014 9:02 PM, Steve Capper wrote:
On Thu, May 01, 2014 at 11:34:16AM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due
On Tuesday, May 06, 2014 7:49 PM, Christoffer Dall wrote:
On Thu, May 01, 2014 at 11:34:19AM +0900, Jungseok Lee wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2.
Both symmetric and asymmetric configurations for page size and
translation
as per Christoffer's comment
- revised arm64 Kconfig help message as per Christoffer's comment
- rebased on top of for-next/core branch of arm64/linux.git
Jungseok Lee (7):
arm64: Use pr_* instead of printk
arm64: Introduce VA_BITS and translation level options
arm64: Add a description on 48
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked
or there is about 512GB RAM.
References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked
This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
arch/arm/include/asm/kvm_mmu.h | 10 +
arch/arm/kvm/arm.c |8
arch/arm/kvm/mmu.c | 77
://www.spinics.net/linux/lists/arm-kernel/msg319552.html
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
Reviewed
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by: Jungseok Lee jays
christoffer.d...@linaro.org
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm/kvm/arm.c | 82 +-
arch/arm64/include/asm/kvm_arm.h | 17 ++--
arch/arm64/kvm/hyp-init.S
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
Please ignore the previous patch since it has a critical error
on KVM_MMU_CACHE_MIN_PAGES.
---
arch/arm/include/asm/kvm_mmu.h | 10 +
arch/arm/kvm/arm.c |8
arch/arm
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
Please ignore the previous patch since it has a critical error
on KVM_MMU_CACHE_MIN_PAGES.
I'm really sorry about noise. My email client terminated
On Tuesday, May 27, 2014 10:54 PM, Christoffer Dall wrote:
On Mon, May 12, 2014 at 06:40:54PM +0900, Jungseok Lee wrote:
This patch sets TCR_EL2.PS, VTCR_EL2.T0SZ and vttbr_baddr_mask in runtime,
not compile time.
In ARMv8, EL2 physical address size (TCR_EL2.PS) and stage2 input address
On Tuesday, May 27, 2014 11:03 PM, Christoffer Dall wrote:
On Tue, May 27, 2014 at 03:53:49PM +0200, Christoffer Dall wrote:
On Mon, May 12, 2014 at 06:40:54PM +0900, Jungseok Lee wrote:
This patch sets TCR_EL2.PS, VTCR_EL2.T0SZ and vttbr_baddr_mask in runtime,
not compile time
On Wednesday, May 28, 2014 5:26 AM, Christoffer Dall wrote:
On Mon, May 12, 2014 at 06:40:44PM +0900, Jungseok Lee wrote:
This patch adds memory layout and translation lookup information about
48-bit address space with 4K pages. The description is based on 4
levels of translation tables
-by: Youngmin Nam youngmin@samsung.com
Good catch.
Reviewed-by: Sachin Kamat sachin.ka...@linaro.org
I've tested it on Exynos5440. It works fine.
Tested-by: Jungseok Lee jays@samsung.com
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message
This patch implements pm_power_off function since a power-down
control register should be set in order to turn off EXYNOS5440.
Otherwise, power domains remain alive despite poweroff action.
Signed-off-by: Jungseok Lee jays@samsung.com
---
arch/arm/mach-exynos/common.c | 17
On Saturday, September 28, 2013 6:26 PM, Sachin Kamat wrote:
On 28 September 2013 10:37, Jungseok Lee jays@samsung.com wrote:
+static void exynos5440_power_off(void)
+{
+ struct device_node *np;
+ void __iomem *addr;
+
+ np = of_find_compatible_node(NULL, NULL
This patch implements pm_power_off function since a power-down
control register should be set in order to turn off EXYNOS5440.
Otherwise, power domains remain alive despite poweroff action.
Signed-off-by: Jungseok Lee jays@samsung.com
---
Changes since v1:
- Added a comment to the effect
On Monday, September 30, 2013 12:04 PM, Sachin Kamat wrote:
On 30 September 2013 07:02, Jungseok Lee jays@samsung.com wrote:
+ /* turn off all power domains */
+ addr = of_iomap(np, 0) + 0x14;
+ __raw_writel(0x1, addr);
Actually my comment was more about
This patch corrects kernel command line handler when io_tlb_nslabs
is set to 0.
A current implementation allocates default size memory (64MB) when
0 is given to io_tlb_nslabs (swiotlb=0) by kernel command line.
In other words, memory is allocated unintentionally.
Signed-off-by: Jungseok Lee jays
On Tuesday, April 01, 2014 9:46 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Apr 01, 2014 at 10:51:58AM +0900, Jungseok Lee wrote:
This patch corrects kernel command line handler when io_tlb_nslabs is
set to 0.
A current implementation allocates default size memory (64MB) when
0 is given
of translation tables for both native, HYP
and stage2 sides.
This series is validated with Fast Models and kvmtool as platform and guest
launcher, respectively.
Jungseok Lee (8):
arm64: Use pr_* instead of printk
arm/arm64: KVM: Fix line length exceeding 80 characters
arm64
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/kernel/traps.c | 14
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
Documentation/arm64
This patch separates page size from level of translation tables in
configuration. It facilitates introduction of different options,
such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
On Monday, April 14, 2014 6:34 PM, Steve Capper wrote:
On Mon, Apr 14, 2014 at 06:24:55PM +0900, Jungseok Lee wrote:
On Monday, April 14, 2014 6:14 PM, Steve Capper wrote:
On Mon, Apr 13, 2014 at 04:41:07PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables
On Tuesday, April 15, 2014 12:14 AM, Steve Capper wrote:
On Mon, Apr 14, 2014 at 04:41:07PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due
On Tuesday, April 15, 2014 1:19 AM, Marc Zyngier wrote:
On 14/04/14 08:40, Jungseok Lee wrote:
This patch deals with checkpatch complaint as fixing line length
exceeding 80 characters.
WARNING: line over 80 characters
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed
On Tuesday, April 15, 2014 1:12 AM, Marc Zyngier wrote:
On 14/04/14 08:41, Jungseok Lee wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4
levels guest can run on ARMv8 architecture as introducing
On Tuesday, April 15, 2014 12:14 AM, Steve Capper wrote:
On Mon, Apr 14, 2014 at 04:41:07PM +0900, Jungseok Lee wrote:
This patch implements 4 levels of translation tables since 3 levels of
page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due
comment
- added a macro for a number of objects of as per Marc's comment
Jungseok Lee (7):
arm64: Use pr_* instead of printk
arm64: Decouple page size from level of translation tables
arm64: Introduce a kernel configuration option for VA_BITS
arm64: Add a description on 48-bit
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/kernel/traps.c | 14
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4 levels
guest can run on ARMv8 architecture as introducing this feature.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
or there is about 512GB RAM.
References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/Kconfig |7 +
arch/arm64/include/asm/memblock.h
This patch adds a kernel configuration for VA_BITS.
It helps to prevent unnecessary #ifdef statements insertions
for VA_BITS when implementing different page sizes and level of
translation tables.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
Documentation/arm64
This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/include/asm/pgtable-4level-hwdef.h | 50 +
arch/arm64/include
This patch separates page size from level of translation tables in
configuration. It facilitates introduction of different options,
such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
On Thursday, April 17, 2014 9:13 PM, Marc Zyngier wrote:
On Wed, Apr 16 2014 at 5:33:31 am BST, Jungseok Lee jays@samsung.com
wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4
levels guest
This patch separates page size from level of translation tables in
configuration. It facilitates introduction of different options,
such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
+ 2 levels host
9) 64KB + 2 levels guest on 64KB + 2 levels host
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm/include/asm/kvm_mmu.h | 10 +
arch/arm/kvm/mmu.c | 88
This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/include/asm/pgtable-4level-hwdef.h | 50 +
arch/arm64/include
or there is about 512GB RAM.
References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/Kconfig |7 +
arch/arm64/include/asm/memblock.h
This patch fixed the following checkpatch complaint as using pr_*
instead of printk.
WARNING: printk() should include KERN_ facility level
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
arch/arm64/kernel/traps.c | 14
This patch adds a kernel configuration for VA_BITS.
It helps to prevent unnecessary #ifdef statements insertions
for VA_BITS when implementing different page sizes and level of
translation tables.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch
This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.
Signed-off-by: Jungseok Lee jays@samsung.com
Reviewed-by: Sungjinn Chung sungjinn.ch...@samsung.com
---
Documentation/arm64
comment
- added a macro for a number of objects of as per Marc's comment
Changes since v2:
- revised some macros in a generic way as per Marc's comment
- added a 2 level option for kvm mmu cache allocation as per Marc's comment
Jungseok Lee (7):
arm64: Use pr_* instead of printk
arm64
://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
The original author Jungseok Lee is no longer available to work on
future versions of these patches. I was thinking that if they didn't
get picked up as they are that with the original author's blessing I
would pick them up and keep
On Jul 16, 2014, at 6:44 AM, Catalin Marinas wrote:
On 15 Jul 2014, at 15:53, Jungseok Lee jungseokle...@gmail.com wrote:
On Jul 15, 2014, at 7:41 AM, Catalin Marinas wrote:
On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
I agree that these patches would be very useful. I just
expression.
+ .efuse_value = 0x5b2d, \
.efuse_value should be incremented by one.
Thanks,
Jungseok Lee
+ .min_efuse_value = 16, \
+ .max_efuse_value = 76, \
+ .first_point_trim = 25, \
+ .second_point_trim = 70, \
+ .default_temp_offset = 25, \
+ .type
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