This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 37 +-
3 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 589ed93..bf72817 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -30,6 +30,8 @@ Required Properties:
which generates global data buses clock and global peripheral buses clock.
- samsung,exynos5433-cmu-g3d - clock controller compatible for CMU_G3D
which generates clocks for 3D Graphics Engine IP.
+ - samsung,exynos5433-cmu-gscl - clock controller compatible for CMU_GSCL
+which generates clocks for GSCALER IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_gscl: clock-controller@0x13cf {
+ compatible = samsung,exynos5433-cmu-gscl;
+ reg = 0x13cf 0x0b10;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index a7f5feb..00dcac3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -540,6 +540,10 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYS_200, aclk_fsys_200, div_aclk_fsys_200,
ENABLE_ACLK_TOP, 18, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_GSCL_111, aclk_gscl_111, div_aclk_gscl_111,
+ ENABLE_ACLK_TOP, 15, 0, 0),
+ GATE(CLK_ACLK_GSCL_333, aclk_gscl_333, div_aclk_gscl_333,
+ ENABLE_ACLK_TOP, 14, 0, 0),
GATE(CLK_ACLK_G2D_266, aclk_g2d_266, div_aclk_g2d_266,
ENABLE_ACLK_TOP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, aclk_g2d_400, div_aclk_g2d_400,
@@ -3223,3 +3227,143 @@ static void __init exynos5433_cmu_g3d_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, samsung,exynos5433-cmu-g3d,
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL0x0300
+#defineMUX_STAT_GSCL 0x0400
+#defineENABLE_ACLK_GSCL0x0800
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#defineENABLE_PCLK_GSCL0x0900
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#defineENABLE_IP_GSCL0 0x0b00
+#defineENABLE_IP_GSCL1 0x0b04
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL00x0b08
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL10x0b0c
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL20x0b10
+
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)= { fin_pll, aclk_gscl_111, };
+PNAME(aclk_gscl_333_user_p)= { fin_pll, aclk_gscl_333, };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, mout_aclk_gscl_111_user,
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER,
