Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Tomasz,
On 3 October 2012 17:25, Tomasz Figa t.f...@samsung.com wrote:
Hi Chander, Thomas,
I think this patch could be split into several smaller, while retaining
logical integrity of particular patches, e.g.:
- the change introduced to __clk_init (with proper description and rationale
why the generic code is being touched)
- generic exynos4 code
- exynos4210-specific code
- exynos4x12-specific code
- patch enabling common clock framework on exynos4.
Also, see some nitpicks inline.
On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
From: Thomas Abraham thomas.abra...@linaro.org
Register clocks for Exynos4 platfotms using common clock framework.
Also included are set of helper functions for clock registration
that can be reused on other Samsung platforms as well.
Cc: Mike Turquette mturque...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/common.h |3 +
arch/arm/mach-exynos/mct.c| 11 +-
arch/arm/plat-samsung/Kconfig |4 +-
drivers/clk/Makefile |1 +
drivers/clk/clk.c | 12 +-
drivers/clk/samsung/Makefile |6 +
drivers/clk/samsung/clk-exynos4.c | 585
+ drivers/clk/samsung/clk.c
| 231 +++
drivers/clk/samsung/clk.h | 190
10 files changed, 1037 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk-exynos4.c
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..4866ec7 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -15,6 +15,7 @@ config ARCH_EXYNOS4
bool SAMSUNG EXYNOS4
default y
select HAVE_SMP
+ select COMMON_CLK
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 SoCs based systems
diff --git a/arch/arm/mach-exynos/common.h
b/arch/arm/mach-exynos/common.h index aed2eeb..2274431 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,9 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
+void exynos4210_clk_init(void);
+void exynos4212_clk_init(void);
exynos4x12_clk_init?
+
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8..a7cace0 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -30,6 +30,8 @@
#include mach/regs-mct.h
#include asm/mach/time.h
+#include common.h
+
#define TICK_BASE_CNT1
enum {
@@ -457,7 +459,7 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = { static void __init exynos4_timer_resources(void)
{
struct clk *mct_clk;
- mct_clk = clk_get(NULL, xtal);
+ mct_clk = clk_get(NULL, fin_pll);
clk_rate = clk_get_rate(mct_clk);
@@ -478,6 +480,13 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
+#ifdef CONFIG_COMMON_CLK
+ if (soc_is_exynos4210())
+ exynos4210_clk_init();
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ exynos4212_clk_init();
exynos4x12_clk_init?
Ok.
+#endif
+
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
diff --git a/arch/arm/plat-samsung/Kconfig
b/arch/arm/plat-samsung/Kconfig index 9c3b90c..35b4cb8 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -26,7 +26,7 @@ config PLAT_S5P
select S5P_GPIO_DRVSTR
select SAMSUNG_GPIOLIB_4BIT
select PLAT_SAMSUNG
- select SAMSUNG_CLKSRC
+ select SAMSUNG_CLKSRC if !COMMON_CLK
select SAMSUNG_IRQ_VIC_TIMER
help
Base platform code for Samsung's S5P series SoC.
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
used by newer systems such as the S3C64XX.
config S5P_CLOCK
- def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+ def_bool ((ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
!COMMON_CLK) help
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6327536..5f5b060 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/
endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
+obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Tomasz,
On 3 October 2012 19:40, Tomasz Figa t.f...@samsung.com wrote:
Hi Chander, Thomas,
I can see one more problem here.
Based on the fact that sdhci-s3c driver receives only the endpoint gate
clock (hsmmc), doesn't the following setup make the driver unable to change
the frequency of this clock?
The driver never changes the clock frequency of the core system clocks
nor of the endpoint. There are internal dividers inside the sdhci
controller which are divide to acheive required clock speed.
Thanks,
Thomas.
On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
+static struct samsung_mux_clock exynos4_mux_clks[] = {
[snip]
+ MUXCLK(exynos4-sdhci.0, mout_mmc0, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 0, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc1, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 4, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc2, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 8, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc3, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 12, 4, 0),
[snip]
+};
+
+static struct samsung_div_clock exynos4_div_clks[] = {
[snip]
+ DIVCLK(exynos4-sdhci.0, div_mmc0, mout_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.0, div_mmc0_pre, div_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1, mout_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1_pre, div_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 24, 8, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2, mout_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2_pre, div_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3, mout_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3_pre, div_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 24, 8, 0),
[snip]
+};
+
+struct samsung_gate_clock exynos4_gate_clks[] = {
[snip]
+ GATECLK(exynos4-sdhci.0, hsmmc0, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 5, hsmmc),
+ GATECLK(exynos4-sdhci.1, hsmmc1, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 6, hsmmc),
+ GATECLK(exynos4-sdhci.2, hsmmc2, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 7, hsmmc),
+ GATECLK(exynos4-sdhci.3, hsmmc3, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 8, hsmmc),
[snip]
+};
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
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Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Sylwester,
Thanks for reviewing this patch series.
On 6 October 2012 00:21, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
Hello,
On 10/01/2012 02:09 PM, chander.kash...@linaro.org wrote:
From: Thomas Abrahamthomas.abra...@linaro.org
Register clocks for Exynos4 platfotms using common clock framework.
Also included are set of helper functions for clock registration
that can be reused on other Samsung platforms as well.
Cc: Mike Turquettemturque...@linaro.org
Cc: Kukjin Kimkgene@samsung.com
Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/common.h |3 +
arch/arm/mach-exynos/mct.c| 11 +-
arch/arm/plat-samsung/Kconfig |4 +-
drivers/clk/Makefile |1 +
drivers/clk/clk.c | 12 +-
drivers/clk/samsung/Makefile |6 +
drivers/clk/samsung/clk-exynos4.c | 585
+
drivers/clk/samsung/clk.c | 231 +++
drivers/clk/samsung/clk.h | 190
10 files changed, 1037 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk-exynos4.c
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
...
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 56e4495..456c50b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1196,6 +1196,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
int __clk_init(struct device *dev, struct clk *clk)
{
int i, ret = 0;
+ u8 index;
struct clk *orphan;
struct hlist_node *tmp, *tmp2;
@@ -1259,6 +1260,7 @@ int __clk_init(struct device *dev, struct clk *clk)
__clk_lookup(clk-parent_names[i]);
}
+
clk-parent = __clk_init_parent(clk);
/*
@@ -1298,11 +1300,13 @@ int __clk_init(struct device *dev, struct clk *clk)
* this clock
*/
hlist_for_each_entry_safe(orphan, tmp, tmp2,clk_orphan_list,
child_node)
- for (i = 0; i orphan-num_parents; i++)
- if (!strcmp(clk-name, orphan-parent_names[i])) {
+ if (orphan-num_parents 1) {
+ index = orphan-ops-get_parent(orphan-hw);
+ if (!strcmp(clk-name, orphan-parent_names[index]))
__clk_reparent(orphan, clk);
- break;
- }
+ } else if (!strcmp(clk-name, orphan-parent_names[0])) {
+ __clk_reparent(orphan, clk);
+ }
As this touches generic code it should rather be put into a separate patch,
along with an explanation why such a change is needed.
There is fix for this in mainline now.
/*
* optional platform-specific magic
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000..69487f7
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,6 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000..74a6f03
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 platforms
+*/
+
+#includelinux/clk.h
+#includelinux/clkdev.h
+#includelinux/io.h
+#includelinux/clk-provider.h
+
+#includeplat/pll.h
+#includeplat/cpu.h
+#includemach/regs-clock.h
+#includemach/sysmmu.h
+#includeplat/map-s5p.h
+
+#include clk.h
+
+#define EXYNOS4_OP_MODE (S5P_VA_CHIPID + 8)
+
+static const char *pll_parent_names[] __initdata = { fin_pll };
+static const char *fin_pll_parents[] __initdata = { xxti, xusbxti };
+static const char *mout_apll_parents[] __initdata = { fin_pll,
fout_apll, };
+static const char *mout_mpll_parents[] __initdata = { fin_pll,
fout_mpll, };
+static const char *mout_epll_parents[] __initdata = { fin_pll,
fout_epll, };
+
+static const char *sclk_ampll_parents[] __initdata = {
+ mout_mpll, sclk_apll, };
+
+static const char *sclk_evpll_parents[] __initdata = {
+ mout_epll, mout_vpll, };
+
+static const char *mout_core_parents[] __initdata = {
+ mout_apll, mout_mpll, };
+
+static const char *mout_mfc_parents[] __initdata = {
+ mout_mfc0, mout_mfc1, };
+
+static const char *mout_dac_parents[] __initdata = {
+
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
On Monday 08 of October 2012 12:04:18 Thomas Abraham wrote: Hi Tomasz, On 3 October 2012 19:40, Tomasz Figa t.f...@samsung.com wrote: Hi Chander, Thomas, I can see one more problem here. Based on the fact that sdhci-s3c driver receives only the endpoint gate clock (hsmmc), doesn't the following setup make the driver unable to change the frequency of this clock? The driver never changes the clock frequency of the core system clocks nor of the endpoint. There are internal dividers inside the sdhci controller which are divide to acheive required clock speed. What is the use of sdhci_cmu_set_clock (which calls clk_set_rate) in sdhci- s3c, then? I think you are missing CLK_SET_RATE_PARENT flags in clocks of which rate can be changed by the driver. Best regards, -- Tomasz Figa Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hello,
On 10/01/2012 02:09 PM, chander.kash...@linaro.org wrote:
From: Thomas Abrahamthomas.abra...@linaro.org
Register clocks for Exynos4 platfotms using common clock framework.
Also included are set of helper functions for clock registration
that can be reused on other Samsung platforms as well.
Cc: Mike Turquettemturque...@linaro.org
Cc: Kukjin Kimkgene@samsung.com
Signed-off-by: Thomas Abrahamthomas.abra...@linaro.org
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/common.h |3 +
arch/arm/mach-exynos/mct.c| 11 +-
arch/arm/plat-samsung/Kconfig |4 +-
drivers/clk/Makefile |1 +
drivers/clk/clk.c | 12 +-
drivers/clk/samsung/Makefile |6 +
drivers/clk/samsung/clk-exynos4.c | 585
+
drivers/clk/samsung/clk.c | 231 +++
drivers/clk/samsung/clk.h | 190
10 files changed, 1037 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk-exynos4.c
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
...
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 56e4495..456c50b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1196,6 +1196,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
int __clk_init(struct device *dev, struct clk *clk)
{
int i, ret = 0;
+ u8 index;
struct clk *orphan;
struct hlist_node *tmp, *tmp2;
@@ -1259,6 +1260,7 @@ int __clk_init(struct device *dev, struct clk *clk)
__clk_lookup(clk-parent_names[i]);
}
+
clk-parent = __clk_init_parent(clk);
/*
@@ -1298,11 +1300,13 @@ int __clk_init(struct device *dev, struct clk *clk)
* this clock
*/
hlist_for_each_entry_safe(orphan, tmp, tmp2,clk_orphan_list,
child_node)
- for (i = 0; i orphan-num_parents; i++)
- if (!strcmp(clk-name, orphan-parent_names[i])) {
+ if (orphan-num_parents 1) {
+ index = orphan-ops-get_parent(orphan-hw);
+ if (!strcmp(clk-name, orphan-parent_names[index]))
__clk_reparent(orphan, clk);
- break;
- }
+ } else if (!strcmp(clk-name, orphan-parent_names[0])) {
+ __clk_reparent(orphan, clk);
+ }
As this touches generic code it should rather be put into a separate patch,
along with an explanation why such a change is needed.
/*
* optional platform-specific magic
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000..69487f7
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,6 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000..74a6f03
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 platforms
+*/
+
+#includelinux/clk.h
+#includelinux/clkdev.h
+#includelinux/io.h
+#includelinux/clk-provider.h
+
+#includeplat/pll.h
+#includeplat/cpu.h
+#includemach/regs-clock.h
+#includemach/sysmmu.h
+#includeplat/map-s5p.h
+
+#include clk.h
+
+#define EXYNOS4_OP_MODE (S5P_VA_CHIPID + 8)
+
+static const char *pll_parent_names[] __initdata = { fin_pll };
+static const char *fin_pll_parents[] __initdata = { xxti, xusbxti };
+static const char *mout_apll_parents[] __initdata = { fin_pll,
fout_apll, };
+static const char *mout_mpll_parents[] __initdata = { fin_pll,
fout_mpll, };
+static const char *mout_epll_parents[] __initdata = { fin_pll,
fout_epll, };
+
+static const char *sclk_ampll_parents[] __initdata = {
+ mout_mpll, sclk_apll, };
+
+static const char *sclk_evpll_parents[] __initdata = {
+ mout_epll, mout_vpll, };
+
+static const char *mout_core_parents[] __initdata = {
+ mout_apll, mout_mpll, };
+
+static const char *mout_mfc_parents[] __initdata = {
+ mout_mfc0, mout_mfc1, };
+
+static const char *mout_dac_parents[] __initdata = {
+ mout_vpll, sclk_hdmiphy, };
+
+static const char *mout_hdmi_parents[] __initdata = {
+ sclk_pixel, sclk_hdmiphy, };
+
+static const char *mout_mixer_parents[]
Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Hi Chander, Thomas,
I can see one more problem here.
Based on the fact that sdhci-s3c driver receives only the endpoint gate
clock (hsmmc), doesn't the following setup make the driver unable to change
the frequency of this clock?
On Monday 01 of October 2012 17:39:21 chander.kash...@linaro.org wrote:
+static struct samsung_mux_clock exynos4_mux_clks[] = {
[snip]
+ MUXCLK(exynos4-sdhci.0, mout_mmc0, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 0, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc1, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 4, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc2, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 8, 4, 0),
+ MUXCLK(exynos4-sdhci.1, mout_mmc3, group1_parents, 0,
+ EXYNOS4_CLKSRC_FSYS, 12, 4, 0),
[snip]
+};
+
+static struct samsung_div_clock exynos4_div_clks[] = {
[snip]
+ DIVCLK(exynos4-sdhci.0, div_mmc0, mout_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.0, div_mmc0_pre, div_mmc0, 0,
+ EXYNOS4_CLKDIV_FSYS1, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1, mout_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.1, div_mmc1_pre, div_mmc1, 0,
+ EXYNOS4_CLKDIV_FSYS1, 24, 8, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2, mout_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 0, 4, 0),
+ DIVCLK(exynos4-sdhci.2, div_mmc2_pre, div_mmc2, 0,
+ EXYNOS4_CLKDIV_FSYS2, 8, 8, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3, mout_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 16, 4, 0),
+ DIVCLK(exynos4-sdhci.3, div_mmc3_pre, div_mmc3, 0,
+ EXYNOS4_CLKDIV_FSYS2, 24, 8, 0),
[snip]
+};
+
+struct samsung_gate_clock exynos4_gate_clks[] = {
[snip]
+ GATECLK(exynos4-sdhci.0, hsmmc0, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 5, hsmmc),
+ GATECLK(exynos4-sdhci.1, hsmmc1, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 6, hsmmc),
+ GATECLK(exynos4-sdhci.2, hsmmc2, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 7, hsmmc),
+ GATECLK(exynos4-sdhci.3, hsmmc3, aclk_133, 0,
+ EXYNOS4_CLKGATE_IP_FSYS, 8, hsmmc),
[snip]
+};
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
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