On Sat, Jul 31, 2010 at 3:09 PM, Kukjin Kim kgene@samsung.com wrote:
MyungJoo Ham wrote:
Many MUX and clock dividers have a status bit so that users can wait
until the status is stable. When corresponding registers are accessed
while a clock is not stable, we may suffer from unexpected
MyungJoo Ham wrote:
Many MUX and clock dividers have a status bit so that users can wait
until the status is stable. When corresponding registers are accessed
while a clock is not stable, we may suffer from unexpected errors.
Therefore, we introduce a mechanism to let the operations
