Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 06/08/2017 11:23 AM, Noam Camus wrote: *> From:* Vineet Gupta *> Sent:* Thursday, June 8, 2017 7:38 PM >> >> With simulator we just turn this configuration on, so we redirect the Legacy >> Synopsys L2 ISR from nSIM into machine check. >> This way we end up

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 06/07/2017 08:29 PM, Noam Camus wrote: *From:* Noam Camus *Sent:* Wednesday, June 7, 2017 8:06:17 PM *To:* Vineet Gupta; linux-snps-arc@lists.infradead.org *Cc:* linux-ker...@vger.kernel.org; Elad Kanfi *Subject:* Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[PATCH 17/35] ARC: defconfig: Cleanup from old Kconfig options

Remove old, dead Kconfig option INET_LRO. It is gone since commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library"). Signed-off-by: Krzysztof Kozlowski --- arch/arc/configs/nps_defconfig | 1 - arch/arc/configs/tb10x_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git

[PATCH 00/35] defconfig: Cleanup from old entries

Hi, While cleaning Samsung ARM defconfigs with savedefconfig, I encountered similar obsolete entries in other files. Except the ARM, no dependencies. For ARM, the rest of patches depend on the first change (otherwise it might not apply cleanly). Best regards, Krzysztof Krzysztof Kozlowski

[PATCH 01/11] ARC: set level of log per CPU during boot to be debug level

From: Noam Camus The reasons are: 1) speeding up boot time, becomes critical for many CPUs machine, e.g. NPS400 with 4K CPUs 2) shorten kernel log at boot time, again easy to scan for large scale machines such NPS400 Signed-off-by: Noam Camus ---

[PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register

From: Elad Kanfi HW bug description: in case of HW thread context switch the dpc configuration of the exiting thread is dragged one cycle into the next thread. In order to avoid the consequences of this bug, the DPC register is set to an initial value, and not changed

[PATCH 00/11] plat-eznps upstream cont. set 2

From: Noam Camus With this patch set I continue the effort of upstreaming the eznps platform for arch/arc. It comprise of couple of patches from last set yet not accepted, patches for HW erratas and some misc extensions such for HIGHMEM / NUMA. This set got more generic

[PATCH 05/11] ARC: Support more than one PGDIR for KVADDR

From: Noam Camus This way FIXMAP can have 2 PTEs per CPU even for NR_CPUS=4096 For the extreme case like in eznps platform We use all gutter between kernel and user. Signed-off-by: Noam Camus --- arch/arc/Kconfig | 11 +++

[PATCH 04/11] ARC: Add CPU topology

From: Noam Camus Now it is used for NPS SoC for multi-core of 256 cores and SMT of 16 HW threads per core. This way with topology the scheduler is much efficient in creating domains and later using them. Signed-off-by: Noam Camus --- arch/arc/Kconfig

[PATCH 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers

From: Noam Camus thread_struct got new field for data plane of eznps platform. This field got place for data plane auxiliary registers and for any extra registers that might be changed in kernel code. We save EFLAGS, and GPA1 auxiliary registers since they may be changed by

[PATCH 10/11] ARC: [plat-eznps] handle dedicated AUX registers

From: Liav Rehana Preserve eflags and gpa1 auxiliaries during exception Registers used by compare exchange instructions. GPA1 is used for compare value, and EFLAGS got bit reflects atomic operation response. EFLAGS is zeroed for each new user task so it won't get its parent

[PATCH 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

From: Noam Camus We add ability for all cores at NPS SoC to control the number of cycles HW thread can execute before it is replace with another eligible HW thread within the same core. The replacement is done by the HE scheduler. Signed-off-by: Noam Camus

[PATCH 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

From: Liav Rehana The following commit adds a config that will enable us to distinguish between building the kernel for platforms that have a different set of auxiliary registers for each cpu and platforms that have a shared set of auxiliary registers across every thread in