On 07/12, Eugeniy Paltsev wrote:
> On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> > On 06/21, Eugeniy Paltsev wrote:
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > > same
> > > dividers and corresponding control registers mapped to different
> > > addresses.
We faced with problem when we tried to utilize 1G DRAM by linux on
HSDK.
We can't use our usual kernel memory address (0x8000) like on
AXS103 because of DCCM memory bank located at exactly same
address (0x8000)
But we can't simply move kernel memory address to another address (like
0x9
Most of the time we indeed use the one and only LINUX_LINK_BASE
set to 0x8000_. But there might be good reasons to move
the kernel to another location like 0x9z etc.
And we want IOC aperture to cover entire area used by the kernel,
so let's make its base matching link base and add required ass
This series introduces some required preparations and initial
port of ARC HS Development Kit board with some basic features such
as serial port, USB, SD/MMC and Ethernet.
Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware periph
From: Alexey Brodkin
This initial port adds support of ARC HS Development Kit board with some
basic features such serial port, USB, SD/MMC and Ethernet.
Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware peripherals.
Note as
On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
> > So we add one common driver for such PLL
