On 07/27, Vineet Gupta wrote:
> Hi Stephen,
>
> On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote:
> >HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
> >dividers and corresponding control registers mapped to different addresses.
> >So we add one common driver for such PLLs.
>
Hi Stephen,
On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote:
HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on HSDK board consist of three divi
