This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++
1 file changed, 41 insertions(+)
creat
"possible_cpus" as we
want it set correctly even if we run kernel on HW which has fewer cores
than expected (or we launch kernel via debugger and kick fever cores
than HW has)
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com&g
As we have option in u-boot to set CPU mask for running linux,
we want to pass information to kernel about CPU cores should
be brought up. So we patch kernel dtb in u-boot to set
possible-cpus property.
This also allows us to have correctly setuped MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
by multiple cpus and mcip doesn't
> guarantee any internal serialization/buffering. Granted, current use
case is fine
> as mcip_setup_per_cpu --> plat_smp_ops.init_per_cpu is serialized by master
> core,
> we could run into issue when say cpu hot plug etc
works. So bet
As we have option in u-boot to set CPU mask for running linux,
we want to pass information to kernel about CPU cores should
be brought up. So we patch kernel dtb in u-boot to set
possible-cpus property.
This also allows us to have correctly setuped MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
This patch series add support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers
are supported.
Eugeniy Paltsev (2):
dmaengine: Introduce DW AXI DMAC driver
dt-bindings: Document the Synopsys
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++
1 file changed, 41 insertions(+)
creat
As for today slc_entire_op with OP_FLUSH command flush and invalidate
SLC entry instead of flush only. Fix that.
NOTE:
As for today we use slc_entire_op only with OP_FLUSH_N_INV command,
so it is kinda preventiv fix.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
V1
As for today slc_entire_op with OP_FLUSH command flush and invalidate
SLC entry instead of flush only. Fix that.
NOTE:
As for today we use slc_entire_op only with OP_FLUSH_N_INV command,
so it is kinda preventiv fix.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/
:
"okay" - The CPU is running; "disabled" - The CPU is in a
quiescent state."
Also we setup MCIP debug mask according cpu possible mask.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/kernel/mcip.c | 10 --
arch/arc/kernel/
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 100 constant.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/ar
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/hsdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/bo
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Signed-off-by: Eugeniy Paltsev
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-hsdk/platform.c | 42 --
1 file changed, 42 del
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll fre
On Tue, 2017-11-14 at 15:46 -0800, sb...@codeaurora.org wrote:
> On 11/14, Alexey Brodkin wrote:
> > Hi Vladimir,
> >
> > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:
> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:
> > > >
> >
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-hsdk/platform.c | 42 --
1 file changed, 42 del
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Signed-off-by: Eugeniy Paltsev
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 100 constant.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/ar
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll fre
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/hsdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/bo
DW ethernet controller on axs10x hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 8
1 file changed, 8 insertions(+)
diff
Use reset controller driver instead of platform quirk for AXS10x boards
to reset DW ethernet controller HW.
Eugeniy Paltsev (2):
ARC: [plat-axs10x]: DTS: Add reset controller node to manage ethernet
reset
ARC: [plat-axs10x]: Remove platform quirk to reset ethernet IP
arch/arc/boot/dts
Remove platform quirk to reset ethernet IP as AXS10x reset driver
(reset-axs10x.c) was applied.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/ar
Hi Stephen, Michael,
Please treat this message as a polite reminder to review my patch.
It would be really nice to see this patch in 4.15.
Thanks.
On Fri, 2017-09-29 at 16:13 +0300, Eugeniy Paltsev wrote:
> Add option to set initial output frequency of plls via
> "clock-frequenc
Increase SDIO CIU frequency from 1250Hz to 5000Hz by
switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
NOTE: This patch can possibly fi
On Thu, 2017-10-05 at 06:04 -0700, Vineet Gupta wrote:
> Hi Eugeniy,
>
> On 09/22/2017 09:49 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on HSDK hangs sometimes after SW reset, so
> > add reset node to make possible to reset DW ethernet controller HW.
> >
radead.org/msg02689.html
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../bindings/clock/snps,hsdk-pll-clock.txt | 5
.../devicetree/bindings/clock/snps,pll-clock.txt | 5
drivers/clk/axs10x/pll_clock.c | 34 +++
Add temporary fix to HSDK platform code to setup CPU frequency
to 1GHz on early boot.
We can remove this fix when smart hsdk pll driver will be
introduced, see discussion:
https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html
Signed-off-by: Eugeniy Paltsev <eugeniy.p
On Wed, 2017-09-27 at 10:40 -0700, Vineet Gupta wrote:
> On 09/22/2017 09:49 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on HSDK hangs sometimes after SW reset, so
> > add reset node to make possible to reset DW ethernet controller HW.
> >
> > Sig
DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v2 -> v3:
* Remove v1 suffix as we finaly got rid of v1 suffix in reset
after reset.
As of today only the following lines are used:
- DW GMAC - line 5
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
* The creg reset register is self-clearing so we don't need to clear it
manually. Fixed it.
* Use reset callbac
On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So def
-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_m
1
to 1250 Hz until we fix dw sdio driver itself.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/hsdk.dts | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 8
On Wed, 2017-09-06 at 12:54 -0700, Vineet Gupta wrote:
> On 09/06/2017 11:21 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on AXS10x hangs sometimes after SW reset, so
> > add temporary quirk to reset DW ethernet controller IP core.
> > This quirk can be removed afte
/9903375/)
will be available in upstream.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index f1ac679..cf14ebc 100644
--- a/ar
Hi Petr,
On Tue, 2017-09-05 at 16:54 +0200, Petr Mladek wrote:
> On Mon 2017-08-28 19:58:07, Eugeniy Paltsev wrote:
> > In the current implementation we take the first console that
> > registers if we didn't select one.
> >
> > But if we specify console via "stdo
Add core pll node (core_clk) to manage cpu frequency.
core_clk node represents pll itself.
input_clk node represents clock signal source (basically xtal)
which comes to pll input.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/hsdk.dts
Hi Philipp,
Do you have plans to add reset-simple driver into 4.14?
It would be nice to use it for AXS10x in 4.14.
Thanks.
On Mon, 2017-08-14 at 13:37 +, Eugeniy Paltsev wrote:
> On Fri, 2017-08-11 at 15:46 +0200, Philipp Zabel wrote:
> > Hi Eugeniy,
> >
> > On Thu
Don't select first registered console if one is specified by the device tree
via the stdout-path (or linux,stdout-path) chosen node properties.
Eugeniy Paltsev (2):
OF: move extern declarations of of_stdout inside ifdef
console: don't select first registered console if stdout-path used
a special case:
tty0 will be registered even if it was specified neither
in "bootargs" nor in "stdout-path".
We had to retain this behavior because a lot of ARM boards (and some
powerpc) rely on it.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Chang
Move extern declarations of "of_stdout" pointer inside "CONFIG_OF"
ifdef to be able to get rid of "CONFIG_OF" ifdef in its usage places.
Acked-by: Rob Herring <r...@kernel.org>
Suggested-by: Steven Rostedt <rost...@goodmis.org>
Signed-off-by: Eug
On Sat, 2017-08-26 at 02:44 +0900, Sergey Senozhatsky wrote:
> On (08/25/17 16:14), Eugeniy Paltsev wrote:
> > In the current implementation we take the first console that
> > registers if we didn't select one.
> >
> > But if we specify console via "stdout-path
plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v3 -> v4:
* Rename HSDKv1 to HSDK
Changes v2 -> v3:
* Add specia
On Tue, 2017-08-22 at 14:44 -0700, Vineet Gupta wrote:
> On 07/12/2017 02:40 AM, Eugeniy Paltsev wrote:
> > Most of the time we indeed use the one and only LINUX_LINK_BASE
> > set to 0x8000_. But there might be good reasons to move
> > the kernel to another location like
On Fri, 2017-08-25 at 11:12 -0400, Steven Rostedt wrote:
> On Fri, 25 Aug 2017 18:00:26 +0300
> Eugeniy Paltsev <eugeniy.palt...@synopsys.com> wrote:
>
> > Move extern declarations of "of_root", "of_chosen", "of_aliases",
> > "of_s
Move extern declarations of "of_root", "of_chosen", "of_aliases",
"of_stdout" pointers inside "CONFIG_OF" ifdef to be able to get rid
of "CONFIG_OF" ifdef in their usage places.
Suggested-by: Steven Rostedt <rost...@goodmis.org
me console
is registered earlier than console is pointed in "stdout-path"
property because console pointed in "stdout-path" property can be add as
preferred quite late - when it's driver is probed.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
kernel
On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Add core pll node (core_clk) to manage cpu frequency.
> > core_clk represents pll itself.
> > input_clk represents clock signal source (basically xtal) which
&
On Tue, 2017-08-22 at 14:40 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
> > in device tree.
> >
> > We add "cpu-freq" only to cpu 0 as all cpus ar
y uart device via "console" parameter in
bootargs:
-->8
chosen {
bootargs = "console=ttyS1"
stdout-path =
};
serial0: uart0@... {}
serial1: uart1@... {} /* serial1 is used as console (ttyS1) */
-
for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v2 -> v3:
* Add special management of arc core interface divider.
C
ud field of earlycon device structure by value of
"current-speed" property from device tree or from options
(if they exist) when we use of_setup_earlycon
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v2 -> v3:
* Use simple_strtoul instead of kstrtoul as
ud field of earlycon device structure by value of
"current-speed" property from device tree or from options
(if they exist) when we use of_setup_earlycon
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
* Use standart property name "current-sp
On Thu, 2017-08-17 at 11:11 +, Eugeniy Paltsev wrote:
> Hi Alexandru,
>
> On Wed, 2017-08-16 at 15:15 -0700, Alexandru Gagniuc wrote:
> > This is split into the SOC bindings, and the board dts. The Endor
> > board is currently an FPGA emulation. Once real, silicon arr
rsion
> + */
> +
> +/* This skeleton is based on the ARC700 CPU */
> +#include "skeleton.dtsi"
Perhaps it is better not to use skeleton.dtsi as we are planning to
get rid of it.
--
Eugeniy Paltsev
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
On Wed, 2017-08-16 at 08:46 -0500, Rob Herring wrote:
> On Wed, Aug 16, 2017 at 6:52 AM, Eugeniy Paltsev
> <eugeniy.palt...@synopsys.com> wrote:
> > Hi Rob,
> >
> > On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> > > On Tue, Aug 15, 2017 at 12:21
Hi Rob,
On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> On Tue, Aug 15, 2017 at 12:21 PM, Eugeniy Paltsev
> <eugeniy.palt...@synopsys.com> wrote:
> > [snip]
> > @@ -282,7 +283,15 @@ int __init of_setup_earlycon(const struc
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
odkin <abrod...@synopsys.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v8 -> v9:
* Revert removing of ARC_PLAT_HSDK (now it is called ARC_SOC_HSDK)
as it breaks uniprocessor configuation build.
* Enable INPUT_EVDEV in hsdk_defconfig as it is required for
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
I'll add this to
[PATCH 3/3 v9] ARC: hsdk: initial port for HSDK board
On Tue, 2017-08-15 at 20:12 +0300, Alexey Brodkin wrote:
> This is required for user-space apps to work with keyboard/mice.
>
> Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
> Cc: Eug
ud field of earlycon device structure by baud value
from device tree or from options (if they exist) when we use
of_setup_earlycon
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/tty/serial/earlycon.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drive
for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
* Remove all MODULE* defines as this driver can't be build
Use cpu's node "cpu-freq" param instead of platform-specific
"/cpu_card/core_clk" as it works only if we use fixed-clock for cpu
clocking.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 12
1 file c
Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
in device tree.
We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
clock source (same pll in our case).
We override cpus node in skeleton as we don't need this change for
nsim.
Signed-off
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/axc003.dtsi | 11 +--
ar
On Fri, 2017-08-11 at 15:46 +0200, Philipp Zabel wrote:
> Hi Eugeniy,
>
> On Thu, 2017-08-10 at 19:41 +0300, Eugeniy Paltsev wrote:
> > ARC AXS10x boards support custom IP-block which allows to control
> > reset signals of selected peripherals. For example DW GMAC,
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
- Remove defines of the unused registers.
Hi Philipp,
On Wed, 2017-07-19 at 17:07 +0200, Philipp Zabel wrote:
> On Tue, 2017-07-18 at 20:25 +0300, Eugeniy Paltsev wrote:
> > The HSDK v1 periphery IPs can be reset by accessing some registers
> > from the CGU block.
> >
> > The list of available reset li
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../bindings/reset/snps,hsdk-v1-reset.txt | 28
MAINT
; load again [reset happens])
Also some reset controllers have only reset callback instead of
assert + deassert callbacks pair, so handle this case.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 -
1 file cha
for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../bindings/clock/snps,hsdkv1-pll-clock.txt | 28 ++
MAINT
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
Note that PAE remapping for DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Eug
On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
>
On Wed, 2017-06-21 at 22:16 +0300, Eugeniy Paltsev wrote:
Hi Stephen, Michael,
Maybe you have any comments or remarks about this patch? And if you
don't could you please apply it.
Thanks a lot!
> AXS10X boards manages it's clocks using various PLLs. These PLL has
> same
>
"sp" register is member of "scratch" structure (which is nested
in user_regs_struct)
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
linux/arc/arch_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux/arc/arch_regs.c b/l
ate a node for each core interrupt controller because
we wouldn't able to specify which one is parent for interrupt
distribution unit:
>>>-
cpus {
cpu@0 { intc@0 };
cpu@1 { intc@1 };
};
interrupt-distribution-unit {
interrupt-parent =
};
&
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
m code.
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Documentation/devicetree/bindings/arc/hsdk.txt | 7 ++
arch/arc/Kconfig | 1 +
arch/arc/Makefile |
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
Signed-off-by: Vlad Zakharov <vzak...@synopsys.com>
Signed-off-by: Jose Abreu <joab...@synopsys.com>
---
Changes for v4:
- fix resource freing after error in of_axs10x_pll_clk_setup
- add axs10x* prefix to main functions a
we can use DMA_CTRL_REUSE flag for all channel types.
Also it allows to test reusing mechanism with simply mem-to-mem dma
test.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
include/linux/dmaengine.h | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff
On Tue, 2017-04-25 at 21:12 +0300, Andy Shevchenko wrote:
> On Tue, 2017-04-25 at 15:16 +0000, Eugeniy Paltsev wrote:
> > On Mon, 2017-04-24 at 19:56 +0300, Andy Shevchenko wrote:
> > > On Mon, 2017-04-24 at 15:55 +0000, Eugeniy Paltsev wrote:
> > > > Hi,
> > &
On Wed, 2017-04-26 at 18:04 +0300, Andy Shevchenko wrote:
> On Tue, 2017-04-25 at 21:12 +0300, Andy Shevchenko wrote:
> > On Tue, 2017-04-25 at 15:16 +, Eugeniy Paltsev wrote:
> > > On Mon, 2017-04-24 at 19:56 +0300, Andy Shevchenko wrote:
> > > > On Mon, 2017
Hi,
On Fri, 2017-04-21 at 18:13 +0300, Andy Shevchenko wrote:
> On Fri, 2017-04-21 at 14:29 +0000, Eugeniy Paltsev wrote:
> > On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote:
> > > On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:
> > > > This pat
itch to virt-dma API (according to previous RFC)
* Small fixies according to previous RFC
* Add DT bindings
Eugeniy Paltsev (2):
dt-bindings: Document the Synopsys DW AXI DMA bindings
dmaengine: Add DW AXI DMAC driver
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 +
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/K
Hi Vinod!
Thanks for respond.
My comments below.
On Tue, 2017-03-14 at 08:30 +0530, Vinod Koul wrote:
> On Tue, Feb 21, 2017 at 11:38:04PM +0300, Eugeniy Paltsev wrote:
>
> > +static void vchan_desc_put(struct virt_dma_desc *vdesc)
> > +{
> > + axi_desc_
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/K
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++
1 file changed, 34 insertions(+)
creat
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