From: Eugeniy Paltsev
Date: Thu, 26 Jul 2018 15:05:37 +0300
> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2
As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
relies on L1 line length (L1_CACHE_BYTES).
This isn't correct in case of system with several cache levels
which might have L1 cache line length smaller than L2 line. This
can lead to sharing one cache line between DMA buffer and
