On Tuesday 01 December 2015 06:59 PM, Marc Zyngier wrote:
>> +static int nps400_irq_map(struct irq_domain *d, unsigned int irq,
>> > +irq_hw_number_t hw)
>> > +{
>> > + switch (irq) {
>> > + case TIMER0_IRQ:
>> > +#if defined(CONFIG_SMP)
>> > + case IPI_IRQ:
>> > +#endif
>> >
From: Marc Zyngier [mailto:marc.zyng...@arm.com]
Sent: Thursday, December 03, 2015 8:34 PM
>>> Silly question: why cannot you just write the actual instruction
>>> instead of shoving the instruction like this? Also, .inst would be
>>> more appropriate...
>> [Noam Camus] Since this is instructio
Hi Noam,
On 02/12/15 15:08, Noam Camus wrote:
>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>> Sent: Tuesday, December 01, 2015 3:29 PM
>
>> + interrupt source. The value shall be 1.
>
>> So you never have to encode the interrupt trigger type? Do you only support
>> edge or level?
> I A
>From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>Sent: Tuesday, December 01, 2015 3:29 PM
> + interrupt source. The value shall be 1.
>So you never have to encode the interrupt trigger type? Do you only support
>edge or level?
I Always use level sensitive.
> +
> +#define NPS_GIM_P_EN 0x100
On 01/12/15 13:02, Noam Camus wrote:
> From: Noam Camus
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC)
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noa
