...@vger.kernel.org; Chris Metcalf; daniel.lezc...@linaro.org;
Thomas Gleixner; Jason Cooper
Subject: Re: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips
Hi Marc,
On Friday 18 December 2015 10:01 PM, Marc Zyngier wrote:
> On 18/12/15 14:29, Noam Camus wrote:
>>> From:
Hi Marc,
On Friday 18 December 2015 10:01 PM, Marc Zyngier wrote:
> On 18/12/15 14:29, Noam Camus wrote:
>>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>>> Sent: Friday, December 18, 2015 1:21 PM
>>
I need this for my per CPU irqs such timer and IPI which do not come
from some ex
On 12/01/16 09:12, Vineet Gupta wrote:
[...]
>> HANDLE_DOMAIN_IRQ is not mandatory at all - a number of architectures
>> had something open-coded in the past (with some drawbacks and/or bugs),
>> and this config option is just one of the ways to get it right.
>>
>> MIPS/PPC perform the reverse lo
On Tuesday 12 January 2016 02:18 PM, Marc Zyngier wrote:
> Hi Vineet,
>
> Sorry I missed that one, it must have been caught in the mother of all
> "mark as read" I did on coming back from holiday.
That was expected - NP :-)
>
> On 12/01/16 07:00, Vineet Gupta wrote:
>> > Hi Marc,
>> >
>> > On We
Hi Vineet,
Sorry I missed that one, it must have been caught in the mother of all
"mark as read" I did on coming back from holiday.
On 12/01/16 07:00, Vineet Gupta wrote:
> Hi Marc,
>
> On Wednesday 30 December 2015 05:05 PM, Vineet Gupta wrote:
>> On Friday 18 December 2015 10:01 PM, Marc Zyngi
Hi Marc,
On Wednesday 30 December 2015 05:05 PM, Vineet Gupta wrote:
> On Friday 18 December 2015 10:01 PM, Marc Zyngier wrote:
>> On 18/12/15 14:29, Noam Camus wrote:
From: Marc Zyngier [mailto:marc.zyng...@arm.com]
Sent: Friday, December 18, 2015 1:21 PM
>>>
> I need this for my p
On Friday 18 December 2015 10:01 PM, Marc Zyngier wrote:
> On 18/12/15 14:29, Noam Camus wrote:
>>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>>> Sent: Friday, December 18, 2015 1:21 PM
>>
I need this for my per CPU irqs such timer and IPI which do not come
from some external dev
>From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>Sent: Friday, December 18, 2015 6:31 PM
>> Note that I am working with ARC (seem alike) here and we do not define
>> CONFIG_HANDLE_DOMAIN_IRQ and do not implement set_handle_irq().
>>
>> So for ARC this reverse mapping is something we can leave
On 18/12/15 14:29, Noam Camus wrote:
>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>> Sent: Friday, December 18, 2015 1:21 PM
>
>>> I need this for my per CPU irqs such timer and IPI which do not come
>>> from some external device but from CPUs. For these IRQs I am calling
>>> to irq_crea
>From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>Sent: Friday, December 18, 2015 1:21 PM
>> I need this for my per CPU irqs such timer and IPI which do not come
>> from some external device but from CPUs. For these IRQs I am calling
>> to irq_create_mapping() from my platform at arch/arc and
On 18/12/15 10:37, Noam Camus wrote:
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Wednesday, December 16, 2015 11:31 AM
>
>>> +static int __init nps400_of_init(struct device_node *node,
>>> +struct device_node *parent)
>>> +{
>>> + if (parent)
>>> +
From: Marc Zyngier [mailto:marc.zyng...@arm.com]
Sent: Wednesday, December 16, 2015 11:31 AM
>> +static int __init nps400_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> +if (parent)
>> +panic("DeviceTree incore ic not a root
On 16/12/15 01:10, Noam Camus wrote:
> From: Noam Camus
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC)
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noa
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