On 3/27/20 11:37 AM, Joseph Myers wrote:
> feupdateenv has to preserve the previously raised exceptions even in the
> FE_DFL_ENV case. It's equivalent to
>
> exc = fetestexcept (FE_ALL_EXCEPT);
> fesetenv (envp);
> feraiseexcept (exc);
Ok.
>> In some places I have following:
>>
>> if
On Fri, 27 Mar 2020, Vineet Gupta via Libc-alpha wrote:
> > The bits to enable exception traps look like dynamic control mode bits to
> > me. In general fegetmode should only need to mask off bits on
> > architectures where the same register has both control and status bits,
> > not on
On 3/26/20 4:22 PM, Joseph Myers wrote:
> On Thu, 12 Mar 2020, Vineet Gupta via Libc-alpha wrote:
>
>> +int
>> +fegetmode (femode_t *modep)
>> +{
>> + unsigned int fpcr;
>> +
>> + _FPU_GETCW (fpcr);
>> + *modep = fpcr >> __FPU_RND_SHIFT;
>
> The bits to enable exception traps look like
On Thu, 12 Mar 2020, Vineet Gupta via Libc-alpha wrote:
> +int
> +fegetmode (femode_t *modep)
> +{
> + unsigned int fpcr;
> +
> + _FPU_GETCW (fpcr);
> + *modep = fpcr >> __FPU_RND_SHIFT;
The bits to enable exception traps look like dynamic control mode bits to
me. In general fegetmode
On 3/25/20 7:06 PM, Joseph Myers wrote:
> On Thu, 12 Mar 2020, Vineet Gupta via Libc-alpha wrote:
>
>> diff --git a/sysdeps/arc/bits/fenv.h b/sysdeps/arc/bits/fenv.h
>
> This is another example of one patch fixing up another. You're using the
> same ABI for both hard and soft float, so the
On Thu, 12 Mar 2020, Vineet Gupta via Libc-alpha wrote:
> diff --git a/sysdeps/arc/bits/fenv.h b/sysdeps/arc/bits/fenv.h
This is another example of one patch fixing up another. You're using the
same ABI for both hard and soft float, so the first patch adding a
bits/fenv.h header should be
Signed-off-by: Vineet Gupta
---
sysdeps/arc/bits/fenv.h |9 +-
sysdeps/arc/fpu/e_sqrt.c| 27 +
sysdeps/arc/fpu/e_sqrtf.c | 27 +
sysdeps/arc/fpu/fclrexcpt.c | 36 +
sysdeps/arc/fpu/fegetenv.c | 37 +
sysdeps/arc/fpu/fegetmode.c
