Re: [PATCH 6/9] ARC: clocksource: DT based probe

2016-02-10 Thread Daniel Lezcano
On 02/08/2016 01:23 PM, Vineet Gupta wrote: On Monday 08 February 2016 05:40 PM, Daniel Lezcano wrote: On 02/02/2016 11:58 AM, Vineet Gupta wrote: - Remove explicit clocksource setup and let it be done by OF framework by defining CLOCKSOURCE_OF_DECLARE() for various timers - This allows

RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

2016-02-10 Thread Noam Camus
>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] >Sent: Wednesday, February 10, 2016 12:55 AM >> pr_err() in case of error just like most drivers around. By "hang" do >> you mean calling panic()? >No. I meant the errors are caught but no action is taken, the execution >continues

Re: [PATCH] mm,thp: khugepaged: call pte flush at the time of collapse

2016-02-10 Thread Kirill A. Shutemov
On Wed, Feb 10, 2016 at 10:26:15AM +0530, Vineet Gupta wrote: > This showed up on ARC when running LMBench bw_mem tests as > Overlapping TLB Machine Check Exception triggered due to STLB entry > (2M pages) overlapping some NTLB entry (regular 8K page). > > bw_mem 2m touches a large chunk of vaddr

[PATCH v4 3/3] irqchip: add nps Internal and external irqchips

2016-02-10 Thread Noam Camus
From: Noam Camus Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network devices.

[PATCH v4 2/3] clocksource: Add NPS400 timers driver

2016-02-10 Thread Noam Camus
From: Noam Camus Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano

[PATCH v4 1/3] soc: Support for EZchip SoC

2016-02-10 Thread Noam Camus
From: Noam Camus This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus --- include/soc/nps/common.h | 150

[PATCH v4 0/3] Adding NPS400 drivers

2016-02-10 Thread Noam Camus
From: Noam Camus Change Log-- v4: clocksource -- Apply all Daniel comments (Thanks) Handle gracefull return and also using clocksoure mmio driver v3: irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource -- Avoid