[PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/page.h| 30 -- arch/arc/include/asm/pgalloc.h | 7 ++- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h index

[PATCH 10/18] ARC: mm: move MMU specific bits out of ASID allocator

And while at it, rewrite commentary on ASID allocator Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu.h | 13 + arch/arc/include/asm/mmu_context.h | 28 +--- arch/arc/mm/tlb.c | 11 --- 3 files changed, 30

[PATCH 03/18] ARC: mm: move mmu/cache externs out to setup.h

Signed-off-by: Vineet Gupta Signed-off-by: Vineet Gupta --- arch/arc/include/asm/cache.h | 4 arch/arc/include/asm/mmu.h | 4 arch/arc/include/asm/setup.h | 12 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arc/include/asm/cache.h

[PATCH 13/18] ARC: mm: disintegrate pgtable.h into levels and flags

- pgtable-bits-arcv2.h (MMU specific page table flags) - pgtable-levels.h (paging levels) No functional changes, but paves way for easy addition of new MMU code with different bits and levels etc Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgtable-bits-arcv2.h | 149

[PATCH 16/18] ARC: mm: support 4 levels of page tables

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/page.h | 11 +++ arch/arc/include/asm/pgalloc.h| 22 + arch/arc/include/asm/pgtable-levels.h | 45 --- arch/arc/mm/fault.c | 2 ++ arch/arc/mm/tlbex.S

[PATCH 14/18] ARC: mm: hack to allow 2 level build with 4 level code

PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-* but only for !__ASSEMBLY__ tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs for CONFIG_PGTABLE_LEVEL={2,3} and works for 4. So add a workaround local to tlbex.S - the proper fix is to change

[PATCH 11/18] ARC: mm: move MMU specific bits out of entry code

Signed-off-by: Vineet Gupta --- arch/arc/kernel/entry.S | 6 -- arch/arc/mm/tlb.c | 3 +++ 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index 2cb8dfe866b6..684efd094520 100644 --- a/arch/arc/kernel/entry.S +++

[PATCH 06/18] ARC: mm: Enable STRICT_MM_TYPECHECKS

In the past I've refrained from doing this (atleast 2 times) due to the slight code bloat due to ABI implications of pte_t etc becoming sttuct Per ARC ABI, functions return struct via memory and not through register r0, even if the struct would fits in register(s) - caller allocates space on

[PATCH 17/18] ARC: mm: vmalloc sync from kernel to user table to update PMD ...

... not PGD vmalloc() sets up the kernel page table (starting from @swapper_pg_dir). But when vmalloc area is accessed in context of a user task, say opening terminal in n_tty_open(), the user page tables need to be synced from kernel page tables so that TLB entry is created in "user context".

[PATCH 15/18] ARC: mm: support 3 levels of page tables

ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte. Forthcoming hw will have multiple levels, so this change preps mm code for same. It is also fun to try multi levels even on soft-walked code to ensure generic mm code is robust to handle. overview 2 levels

[PATCH 08/18] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgalloc.h | 21 ++--- arch/arc/include/asm/pgtable.h | 6 -- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h index a32ca3104ced..356237b9c537

[PATCH 00/18] ARC mm updates to support 3 or 4 levels of paging

Hi, Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based cores). Most of these changes are incremental cleanups to make way for 14/18 and 15/18 which actually imeplement the new levels (in existing ARCv2

[PATCH 02/18] ARC: mm: remove tlb paranoid code

This was used way back when in arc700 debugging when ASID allocator was still bit flaky. Not needed in last 5 years Signed-off-by: Vineet Gupta Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 3 --- arch/arc/include/asm/mmu.h | 6 - arch/arc/mm/tlb.c | 40

[PATCH 04/18] ARC: mm: remove pgd_offset_fast

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgtable.h | 23 --- arch/arc/mm/fault.c| 2 +- 2 files changed, 1 insertion(+), 24 deletions(-) diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 0c3e220bd2b4..80b57c14b430

[PATCH 12/18] ARC: mm: disintegrate mmu.h (arcv2 bits out)

non functional change Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu-arcv2.h | 94 ++ arch/arc/include/asm/mmu.h | 72 +-- arch/arc/include/asm/mmu_context.h | 1 + arch/arc/include/asm/pgtable.h | 6 --

[PATCH 05/18] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS

Signed-off-by: Vineet Gupta --- arch/arc/mm/tlb.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 6079dfd129b9..15cbc285b0de 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -71,7 +71,7 @@ static void

[PATCH 07/18] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

and remove the one off uncached definition for ARC Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgtable.h | 3 --- arch/arc/mm/ioremap.c | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index

[PATCH 18/18] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd, pud, pmd entries

ARCv3 hardware walker expects Table Descriptors to have b'11 in LSB bits to continue moving to next level. This commits adds that (to ARCv2 code) and ensures that it works in software walked regime. The pte entries stil need tagging, but that is not possible in ARCv2 since the LSB 2 bits are

[PATCH 01/18] ARC: mm: simplify mmu scratch register assingment to mmu needs

ARC700 SMP uses MMU scratch reg for re-entrant interrupt handling (as opposed to the canonical usage for task pgd pointer caching for ARCv2 and ARC700 UP builds). However this requires fabricating a #define in a header which has usual issues of dependency nesting and ugliness. So clean this up

Re: [PATCH 07/18] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

On Tue, Aug 10, 2021 at 05:42:47PM -0700, Vineet Gupta wrote: > and remove the one off uncached definition for ARC > > Signed-off-by: Vineet Gupta > --- > arch/arc/include/asm/pgtable.h | 3 --- > arch/arc/mm/ioremap.c | 3 ++- > 2 files changed, 2 insertions(+), 4 deletions(-) > >

Re: [PATCH 03/18] ARC: mm: move mmu/cache externs out to setup.h

Hi Vineet, On Tue, Aug 10, 2021 at 05:42:43PM -0700, Vineet Gupta wrote: > Signed-off-by: Vineet Gupta Hmm, this one seems odd. Try https://www.kernel.com/ ;-) > Signed-off-by: Vineet Gupta > --- > arch/arc/include/asm/cache.h | 4 > arch/arc/include/asm/mmu.h | 4 >

[GIT PULL] ARC updates for 5.14-rc6

Hi Linus, ARC fixes for 5.14-rc6. Please pull. Thx, -Vineet > The following changes since commit c500bee1c5b2f1d59b1081ac879d73268ab0ff17:   Linux 5.14-rc4 (2021-08-01 17:04:17 -0700) are available in the Git repository at:  

Re: [PATCH 04/18] ARC: mm: remove pgd_offset_fast

On Tue, Aug 10, 2021 at 05:42:44PM -0700, Vineet Gupta wrote: > Signed-off-by: Vineet Gupta > --- > arch/arc/include/asm/pgtable.h | 23 --- > arch/arc/mm/fault.c| 2 +- > 2 files changed, 1 insertion(+), 24 deletions(-) Shouldn't this be a part of the patch

Re: [GIT PULL] ARC updates for 5.14-rc6

The pull request you sent on Tue, 10 Aug 2021 16:21:30 -0700: > git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ > tags/arc-5.14-rc6 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/761c6d7ec820f123b931e7b8ef7ec7c8564e450f Thank you! -- Deet-doot-dot, I