Re: [PATCH 2/2] ARC: [axs10x] Specify reserved memory for frame buffer

2016-04-27 Thread Vineet Gupta 
On Wednesday 27 April 2016 08:05 PM, Alexey Brodkin wrote:
> Allocation of a frame buffer memory in a special memory region
> allows bypassing of so-called IO Coherency aperture
> which is typically set as a range 0x8z-0xAz.
> 
> I.e. all data traffic to PGU bypasses IO Coherency block
> and saves its bandwidth for other peripherals.
> 
> Even though for AXS101 (which sorts ARC770 CPU) IOC is not
> an option for a sake of keeping one DT description for the
> base-board (axs10x_mb.dtsi) we're still defining reserved
> memory location in the very end of DDR.
> 
> Signed-off-by: Alexey Brodkin 
> Cc: devicet...@vger.kernel.org
> ---
>  arch/arc/boot/dts/axc001.dtsi | 20 +++-
>  arch/arc/boot/dts/axc003.dtsi | 14 ++
>  arch/arc/boot/dts/axc003_idu.dtsi | 14 ++
>  arch/arc/boot/dts/axs10x_mb.dtsi  |  2 +-
>  4 files changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
> index 420dcfd..ae6162d 100644
> --- a/arch/arc/boot/dts/axc001.dtsi
> +++ b/arch/arc/boot/dts/axc001.dtsi
> @@ -95,6 +95,24 @@
>   #size-cells = <1>;
>   ranges = <0x 0x8000 0x4000>;
>   device_type = "memory";
> - reg = <0x8000 0x2000>;  /* 512MiB */
> + reg = <0x8000 0x1f00>;  /* 512 - 16 MiB */

Is 16MB fixed size or is this a function of display resolution / density etc.

> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /*
> +  * We just move frame buffer area to the very end of
> +  * available DDR. And even though in case of ARC770 there's
> +  * no strict requirement for a frame-buffer to be in any
> +  * particular location it allows us to use the same
> +  * base board's DT node for ARC PGU as for ARc HS38.
> +  */
> + frame_buffer: frame_buffer@9f00 {
> + compatible = "shared-dma-pool";
> + reg = <0x9f00 0x100>;
> + no-map;
> + };
>   };
>  };
> diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
> index f90fadf..c7a95c2 100644
> --- a/arch/arc/boot/dts/axc003.dtsi
> +++ b/arch/arc/boot/dts/axc003.dtsi
> @@ -100,4 +100,18 @@
>   device_type = "memory";
>   reg = <0x8000 0x2000>;  /* 512MiB */
>   };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /*
> +  * Move frame buffer out of IOC aperture (0x8z-0xAz).
> +  */
> + frame_buffer: frame_buffer@a000 {
> + compatible = "shared-dma-pool";
> + reg = <0xa000 0x100>;

Can this be made a bit more future safe. AXS103 has 1 GB of DDR while kernel
currently only uses 512M. Once we increase that, this will need fixing too. 
Better
to make this as far possible. Note that the IOC start alignment needs to follow
max(4k, size). What will be maximum size of frame buffer - 16M always !

Same for the idu DT below !

> + no-map;
> + };
> + };
>  };
> diff --git a/arch/arc/boot/dts/axc003_idu.dtsi 
> b/arch/arc/boot/dts/axc003_idu.dtsi
> index 06a9f29..929ec8c 100644
> --- a/arch/arc/boot/dts/axc003_idu.dtsi
> +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> @@ -123,4 +123,18 @@
>   device_type = "memory";
>   reg = <0x8000 0x2000>;  /* 512MiB */
>   };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + /*
> +  * Move frame buffer out of IOC aperture (0x8z-0xAz).
> +  */
> + frame_buffer: frame_buffer@a000 {
> + compatible = "shared-dma-pool";
> + reg = <0xa000 0x100>;
> + no-map;
> + };
> + };
>  };
> diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi 
> b/arch/arc/boot/dts/axs10x_mb.dtsi
> index 823f15c..64b063d 100644
> --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> @@ -283,7 +283,7 @@
>   encoder-slave = <>;
>   clocks = <>;
>   clock-names = "pxlclk";
> -
> + memory-region = <_buffer>;
>   port {
>   pgu_output: endpoint {
>   remote-endpoint = <_input>;
> 


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Re: [PATCH 2/2 v6] ASoC: dwc: Update DOCUMENTATION for I2S Driver

2016-04-27 Thread Mark Brown 
On Wed, Apr 27, 2016 at 06:32:42PM +0100, Jose Abreu wrote:
> Hi Mark,
> 
> Sorry. Follows bellow.
> 
> On 27-04-2016 11:05, Jose Abreu wrote:

I can't apply a quote of a patch, please resend.


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[PATCH 2/2] ARC: [axs10x] Specify reserved memory for frame buffer

2016-04-27 Thread Alexey Brodkin 
Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a range 0x8z-0xAz.

I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.

Even though for AXS101 (which sorts ARC770 CPU) IOC is not
an option for a sake of keeping one DT description for the
base-board (axs10x_mb.dtsi) we're still defining reserved
memory location in the very end of DDR.

Signed-off-by: Alexey Brodkin 
Cc: devicet...@vger.kernel.org
---
 arch/arc/boot/dts/axc001.dtsi | 20 +++-
 arch/arc/boot/dts/axc003.dtsi | 14 ++
 arch/arc/boot/dts/axc003_idu.dtsi | 14 ++
 arch/arc/boot/dts/axs10x_mb.dtsi  |  2 +-
 4 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
index 420dcfd..ae6162d 100644
--- a/arch/arc/boot/dts/axc001.dtsi
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -95,6 +95,24 @@
#size-cells = <1>;
ranges = <0x 0x8000 0x4000>;
device_type = "memory";
-   reg = <0x8000 0x2000>;  /* 512MiB */
+   reg = <0x8000 0x1f00>;  /* 512 - 16 MiB */
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   /*
+* We just move frame buffer area to the very end of
+* available DDR. And even though in case of ARC770 there's
+* no strict requirement for a frame-buffer to be in any
+* particular location it allows us to use the same
+* base board's DT node for ARC PGU as for ARc HS38.
+*/
+   frame_buffer: frame_buffer@9f00 {
+   compatible = "shared-dma-pool";
+   reg = <0x9f00 0x100>;
+   no-map;
+   };
};
 };
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index f90fadf..c7a95c2 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -100,4 +100,18 @@
device_type = "memory";
reg = <0x8000 0x2000>;  /* 512MiB */
};
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   /*
+* Move frame buffer out of IOC aperture (0x8z-0xAz).
+*/
+   frame_buffer: frame_buffer@a000 {
+   compatible = "shared-dma-pool";
+   reg = <0xa000 0x100>;
+   no-map;
+   };
+   };
 };
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi 
b/arch/arc/boot/dts/axc003_idu.dtsi
index 06a9f29..929ec8c 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -123,4 +123,18 @@
device_type = "memory";
reg = <0x8000 0x2000>;  /* 512MiB */
};
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   /*
+* Move frame buffer out of IOC aperture (0x8z-0xAz).
+*/
+   frame_buffer: frame_buffer@a000 {
+   compatible = "shared-dma-pool";
+   reg = <0xa000 0x100>;
+   no-map;
+   };
+   };
 };
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 823f15c..64b063d 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -283,7 +283,7 @@
encoder-slave = <>;
clocks = <>;
clock-names = "pxlclk";
-
+   memory-region = <_buffer>;
port {
pgu_output: endpoint {
remote-endpoint = <_input>;
-- 
2.5.5


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[PATCH 0/2] drm/arcpgu: Get use of dedicated memory area for frame buffer

2016-04-27 Thread Alexey Brodkin 
This mini-series allows to allocate frame buffer memory in desired
location. Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture which is typically set
as a range 0x8z-0xAz.

I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.

Cc: Cc: Dave Airlie 
Cc: Daniel Vetter 
Cc: devicet...@vger.kernel.org

Alexey Brodkin (2):
  drm/arcpgu: use dedicated memory area for frame buffer
  ARC: [axs10x] Specify reserved memory for frame buffer

 arch/arc/boot/dts/axc001.dtsi | 20 +++-
 arch/arc/boot/dts/axc003.dtsi | 14 ++
 arch/arc/boot/dts/axc003_idu.dtsi | 14 ++
 arch/arc/boot/dts/axs10x_mb.dtsi  |  2 +-
 drivers/gpu/drm/arc/arcpgu_drv.c  |  6 ++
 5 files changed, 54 insertions(+), 2 deletions(-)

-- 
2.5.5


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[PATCH 0/2 v6] Add I2S audio support for ARC AXS10x boards

2016-04-27 Thread Jose Abreu 
ARC AXS10x platforms consist of a mainboard with several peripherals.
One of those peripherals is an HDMI output port controlled by the ADV7511
transmitter.

This patch set adds I2S audio for the AXS10x platform.

Changes v5 -> v6
* Use SNDRV_DMA_TYPE_CONTINUOUS

Changes v4 -> v5
* Resolve undefined references when compiling as module
* Dropped adv7511 audio patches
* Use DMA properties in I2S to check which mode to use: PIO or DMA (as 
suggested by Lars-Peter Clausen)

Changes v3 -> v4:
* Reintroduced custom PCM driver (see note below)
* Use DT boolean to switch between ALSA DMA engine PCM or custom PCM
* Use fifo depth to program I2S FCR
* Update I2S documentation

Changes v2 -> v3:
* Removed pll_config functions (as suggested by Alexey Brodkin)
* Removed HDMI start at adv7511_core (as suggested by Archit Taneja)
* Use NOP functions for adv7511_audio (as suggested by Archit Taneja)
* Added adv7511_audio_exit() function (as suggested by Archit Taneja)
* Moved adv7511 to its own folder (as suggested by Archit Taneja)
* Separated file rename of adv7511_core (as suggested by Emil Velikov)
* Compile adv7511 as module if ALSA SoC is compiled as module
* Load adv7511 audio only if declared in device tree (as suggested by Laurent 
Pinchart)
* Dropped custom platform driver, using now ALSA DMA engine
* Dropped IRQ handler for I2S

Changes v1 -> v2:
* DT bindings moved to separate patch (as suggested by Alexey Brodkin)
* Removed defconfigs entries (as suggested by Alexey Brodkin)


NOTE:
Although the mainline I2S driver uses ALSA DMA engine,
this controller can be built without DMA support so it
was necessary to add this custom platform driver so that
HDMI audio works in AXS boards.

Cc: Carlos Palminha 
Cc: Mark Brown 
Cc: Liam Girdwood 
Cc: Jaroslav Kysela 
Cc: Takashi Iwai 
Cc: Rob Herring 
Cc: Alexey Brodkin 
Cc: linux-snps-arc@lists.infradead.org
Cc: alsa-de...@alsa-project.org
Cc: devicet...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org

Jose Abreu (2):
  ASoC: dwc: Add custom PCM driver
  ASoC: dwc: Update DOCUMENTATION for I2S Driver

 .../devicetree/bindings/sound/designware-i2s.txt   |   9 +-
 sound/soc/dwc/Kconfig  |   9 +
 sound/soc/dwc/Makefile |   1 +
 sound/soc/dwc/designware.h |  71 +++
 sound/soc/dwc/designware_i2s.c |  94 ++---
 sound/soc/dwc/designware_pcm.c | 228 +
 6 files changed, 383 insertions(+), 29 deletions(-)
 create mode 100644 sound/soc/dwc/designware.h
 create mode 100644 sound/soc/dwc/designware_pcm.c

-- 
1.9.1



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[PATCH 2/2 v6] ASoC: dwc: Update DOCUMENTATION for I2S Driver

2016-04-27 Thread Jose Abreu 
This patch updates documentation for the Designware I2S
driver.

Signed-off-by: Jose Abreu 
Acked-by: Rob Herring 
Cc: Rob Herring 
Cc: Carlos Palminha 
Cc: Alexey Brodkin 
Cc: devicet...@vger.kernel.org
Cc: linux-snps-arc@lists.infradead.org
Cc: alsa-de...@alsa-project.org
Cc: linux-ker...@vger.kernel.org
---

No changes v5 -> v6.

Changes v4 -> v5:
* interrupts is now required property
* Drop 'snps-use-dmaengine' property

This patch was only introduced in v4.

 Documentation/devicetree/bindings/sound/designware-i2s.txt | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt 
b/Documentation/devicetree/bindings/sound/designware-i2s.txt
index 7bb5424..27a728f 100644
--- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/designware-i2s.txt
@@ -3,14 +3,18 @@ DesignWare I2S controller
 Required properties:
  - compatible : Must be "snps,designware-i2s"
  - reg : Must contain the I2S core's registers location and length
+ - interrupts:  where IRQ is the interrupt number.
  - clocks : Pairs of phandle and specifier referencing the controller's
clocks. The controller expects one clock: the clock used as the sampling
rate reference clock sample.
  - clock-names : "i2sclk" for the sample rate reference clock.
+
+Optional properties:
  - dmas: Pairs of phandle and specifier for the DMA channels that are used by
the core. The core expects one or two dma channels: one for transmit and
-   one for receive.
- - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
+   one for receive. Set this parameter if the I2S DMA block is enabled.
+ - dma-names : "tx" for the transmit channel, "rx" for the receive channel. Set
+   this parameter if the I2S DMA block is enabled.
 
 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
 properties please check:
@@ -23,6 +27,7 @@ Example:
soc_i2s: i2s@7ff9 {
compatible = "snps,designware-i2s";
reg = <0x0 0x7ff9 0x0 0x1000>;
+   interrupts = <15>;
clocks = <_i2sclk 0>;
clock-names = "i2sclk";
#sound-dai-cells = <0>;
-- 
1.9.1



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