On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
>
> Signed-off-by: Yuriy Kolerov
> ---
> arch/arc/include/asm/arcregs.h | 11 +++
> arch/arc/kernel/intc-a
On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> After reset all interrupts in the core interrupt controller has
> the highest priority P0. If the platform supports Fast IRQs and
> has more than 1 banks of registers then CPU automatically switch
> banks of registers when P0 interrupt comes.
>
> The
On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> This enhancement allows to mask all available common interrupts
> in IDU interrupt controller in boot time since the kernel can
> discover a number of them from the build register. Also now there
> is no need to specify in device tree a list of used co
On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> When you set a value of ARC_NUMBER_OF_INTERRUPTS option
> it affects only a size of the interrupts table but macros
> for number of virtual interrupts (NR_IRQS) and for number
> of hardware interrupts (NR_CPU_IRQS) remain unchanged.
> Moreover usage of
On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
>
> Signed-off-by: Yuriy Kolerov
Applied to for-next.
Thx,
-Vineet
_
Hello Alexey
On 1/31/2017 2:24 PM, Alexey Brodkin wrote:
Hi Giuseppe,
On Tue, 2017-01-31 at 10:55 +0100, Giuseppe CAVALLARO wrote:
On 1/27/2017 11:23 AM, Alexey Brodkin wrote:
That's why my initial proposal was to ignore whatever we read from this register
if we have MDIO bus instantiated al
Hi Giuseppe,
On Tue, 2017-01-31 at 10:55 +0100, Giuseppe CAVALLARO wrote:
> On 1/27/2017 11:23 AM, Alexey Brodkin wrote:
> >
> > That's why my initial proposal was to ignore whatever we read from this
> > register
> > if we have MDIO bus instantiated already.
>
> sorry for my late reply, I agre
After reset all interrupts in the core interrupt controller has
the highest priority P0. If the platform supports Fast IRQs and
has more than 1 banks of registers then CPU automatically switch
banks of registers when P0 interrupt comes.
The problem is that the kernel expects that by default switch
When you set a value of ARC_NUMBER_OF_INTERRUPTS option
it affects only a size of the interrupts table but macros
for number of virtual interrupts (NR_IRQS) and for number
of hardware interrupts (NR_CPU_IRQS) remain unchanged.
Moreover usage of ARC_NUMBER_OF_INTERRUPTS is bad for
portability since
A summary:
* Use build registers for getting numbers of interrupts both for
core interrupt controller and for IDU interrupt controller.
* Set a default priority for all core interrupt to prevent
unexpected switching of banks of registers.
* Remove option for setting number of interru
Also add new macro ARC_REG_STATUS32 for the address of STATUS32
auxiliary register. It is better to use it instead of magic numbers.
Signed-off-by: Yuriy Kolerov
---
arch/arc/include/asm/arcregs.h | 11 +++
arch/arc/kernel/intc-arcv2.c | 10 ++
2 files changed, 13 insertions(+)
This enhancement allows to mask all available common interrupts
in IDU interrupt controller in boot time since the kernel can
discover a number of them from the build register. Also now there
is no need to specify in device tree a list of used core interrupts
by IDU. E.g. before:
idu_intc: idu
On 1/27/2017 11:23 AM, Alexey Brodkin wrote:
That's why my initial proposal was to ignore whatever we read from this register
if we have MDIO bus instantiated already.
sorry for my late reply, I agree with this approach, according to the
HW and platform configuration the driver has to understan
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