Re: [PATCH] clocksource: arc_timer: RTC: allow registration despite SMP

Hi Daniel, Sorry for delayed response, was away from Linux for a bit :-( On 02/02/2017 06:27 AM, Daniel Lezcano wrote: > On Wed, Feb 01, 2017 at 04:50:15PM -0800, Vineet Gupta wrote: >> So far we didn't allow CPU private 64-bit RTC timer to register in SMP >> as the individual counters may not

[PATCH v1 2/2] dmaengine: Add DW AXI DMAC driver

This patch adds support for the DW AXI DMAC controller. DW AXI DMAC is a part of upcoming development board from Synopsys. In this driver implementation only DMA_MEMCPY and DMA_SG transfers are supported. Signed-off-by: Eugeniy Paltsev --- drivers/dma/Kconfig

[PATCH v1 1/2] dt-bindings: Document the Synopsys DW AXI DMA bindings

This patch adds documentation of device tree bindings for the Synopsys DesignWare AXI DMA controller. Signed-off-by: Eugeniy Paltsev --- .../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++ 1 file changed, 34 insertions(+) create mode

[PATCH v2] clk/axs10x: introduce AXS10X pll driver

AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed