Hi Daniel,
Sorry for delayed response, was away from Linux for a bit :-(
On 02/02/2017 06:27 AM, Daniel Lezcano wrote:
> On Wed, Feb 01, 2017 at 04:50:15PM -0800, Vineet Gupta wrote:
>> So far we didn't allow CPU private 64-bit RTC timer to register in SMP
>> as the individual counters may not be
This patch series add support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Changes for v1:
* Implement Runtime PM (the driver can operate with or without
Ru
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Signed-off-by: Eugeniy Paltsev
---
drivers/dma/Kconfig| 10 +
drivers/d
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev
---
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/b
AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed us
Hello,
I am trying to implement a cpufreq driver for ARCHS cpu.
And I faced with one question I am not able to answer myself. cpufreq framework
allows us using cpufreq frequency tables
that store available for current policy range of frequencies with any
additional data. As I understand for exa
