Re: [PATCH v2 06/30] arc: Implement the new page table range API

On 2/27/23 09:57, Matthew Wilcox (Oracle) wrote: Add set_ptes(), update_mmu_cache_range(), flush_dcache_folio() and flush_icache_pages(). Change the PG_dc_clean flag from being per-page to per-folio (which means it cannot always be set as we don't know that all pages in this folio were

[PATCH v7 13/41] mm: Make pte_mkwrite() take a VMA

The x86 Control-flow Enforcement Technology (CET) feature includes a new type of memory called shadow stack. This shadow stack memory has some unusual properties, which requires some core mm changes to function properly. One of these unusual properties is that shadow stack memory is writable, but

Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE

Hi David, On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand wrote: > /* > * Externally used page protection values. > diff --git a/arch/microblaze/include/asm/pgtable.h > b/arch/microblaze/include/asm/pgtable.h > index 42f5988e998b..7e3de54bf426 100644 > ---

[PATCH v2 06/30] arc: Implement the new page table range API

Add set_ptes(), update_mmu_cache_range(), flush_dcache_folio() and flush_icache_pages(). Change the PG_dc_clean flag from being per-page to per-folio (which means it cannot always be set as we don't know that all pages in this folio were cleaned). Enhance the internal flush routines to take the

Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE

/* * Externally used page protection values. diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index 42f5988e998b..7e3de54bf426 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -131,10 +131,10 @@

Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE

Hi David, On Mon, Feb 27, 2023 at 2:31 PM David Hildenbrand wrote: > On 26.02.23 21:13, Geert Uytterhoeven wrote: > > On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand wrote: > >> Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit > >> from the type. Generic MM currently only uses

Re: [Intel-gfx] [PATCH v5 0/7] Introduce __xchg, non-atomic xchg

On Thu, Feb 23, 2023 at 10:24:19PM +0100, Andrzej Hajda wrote: > On 22.02.2023 18:04, Peter Zijlstra wrote: > > On Wed, Jan 18, 2023 at 04:35:22PM +0100, Andrzej Hajda wrote: > > > > > Andrzej Hajda (7): > > >arch: rename all internal names __xchg to __arch_xchg > > >linux/include: add

Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE

On 26.02.23 21:13, Geert Uytterhoeven wrote: Hi David, Hi Geert, On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand wrote: Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit from the type. Generic MM currently only uses 5 bits for the type (MAX_SWAPFILES_SHIFT), so the stolen

Re: [Intel-gfx] [PATCH v5 5/7] io_uring: use __xchg if possible

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:48PM +0100, Andrzej Hajda wrote: > Recently introduced helper simplifies the code. > > Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Thanks, Andi ___ linux-snps-arc mailing list

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: use __xchg instead of internal helper

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:50PM +0100, Andrzej Hajda wrote: > Prefer core helper if available. > > Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Thanks, Andi ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org

Re: [Intel-gfx] [PATCH v5 6/7] qed: use __xchg if possible

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:49PM +0100, Andrzej Hajda wrote: > Recently introduced helper simplifies the code. > > Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Thanks, Andi ___ linux-snps-arc mailing list

Re: [Intel-gfx] [PATCH v5 4/7] llist: simplify __llist_del_all

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:47PM +0100, Andrzej Hajda wrote: > llist_del_all uses xchg, let's use __xchg here. > > Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Thanks, Andi ___ linux-snps-arc mailing list

Re: [Intel-gfx] [PATCH v5 3/7] arch/*/uprobes: simplify arch_uretprobe_hijack_return_addr

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:46PM +0100, Andrzej Hajda wrote: > In all architectures, except x86, arch_uretprobe_hijack_return_addr > is just __xchg. > > Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Thanks, Andi ___

Re: [Intel-gfx] [PATCH v5 2/7] linux/include: add non-atomic version of xchg

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:45PM +0100, Andrzej Hajda wrote: > The pattern of setting variable with new value and returning old > one is very common in kernel. Usually atomicity of the operation > is not required, so xchg seems to be suboptimal and confusing in > such cases. > >

Re: [Intel-gfx] [PATCH v5 1/7] arch: rename all internal names __xchg to __arch_xchg

Hi Andrzej, On Wed, Jan 18, 2023 at 04:44:44PM +0100, Andrzej Hajda wrote: > __xchg will be used for non-atomic xchg macro. > > Signed-off-by: Andrzej Hajda > Reviewed-by: Arnd Bergmann > Acked-by: Geert Uytterhoeven [m68k] > Acked-by: Palmer Dabbelt [riscv] Reviewed-by: Andi Shyti