On Fri, Dec 08, 2023 at 04:33:44PM -0800, Vineet Gupta wrote:
> On 11/27/23 22:22, Dan Carpenter wrote:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> > master
> > head: 2cc14f52aeb78ce3f29677c2de1f06c0e91471ab
> > commit:
On 11/27/23 22:22, Dan Carpenter wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 2cc14f52aeb78ce3f29677c2de1f06c0e91471ab
> commit: fad84e39f116035ae8d550c6020107b8ac113b45 ARC: boot log: eliminate
> struct cpuinfo_arc #4: boot log per ISA
>
- PUSHAUX/POPAUX helpers to ARCompact entry
- use gas provided "push"/pop pseudo instructions
Signed-off-by: Vineet Gupta
---
arch/arc/include/asm/entry-compact.h | 55 ++-
arch/arc/include/asm/entry.h | 66
2 files changed, 54
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202311280906.vaiweaft-...@intel.com/
Signed-off-by: Vineet Gupta
---
arch/arc/kernel/setup.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arc/kernel/setup.c
Legacy ARC700 processors (first generation of MMU enabled ARC cores) had
VIPT cached which could be configured such that they could alias.
Corresponding support in kernel (with all the obnoxious cache flush overhead)
was added in ARC port 10 years ago to support 1 silicon. That is long bygone
and
Hi,
A pile of accrued changes, compile tested only.
Please test.
Thx,
-Vineet
Vineet Gupta (5):
ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper
ARC: entry: move ARCompact specific bits out of entry.h
ARC: mm: retire support for aliasing VIPT D$
ARC: fix spare error
ARC: fix
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202312082320.vdn5a9hb-...@intel.com/
Signed-off-by: Vineet Gupta
---
arch/arc/kernel/signal.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arc/kernel/signal.c
And for ARcompact variant replace the PUSH/POP macros with gas provided
push/pop pseudo-instructions
This allows ISA specific implementation
e.g. Current ARCv2 PUSH/POP could be replaced with STD/LDL to save 2
registers at a time (w/o bothering with SP update each time) or
perhaps use
(https://download.01.org/0day-ci/archive/20231208/202312082320.vdn5a9hb-...@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce:
(https://download.01.org/0day-ci/archive/20231208/202312082320.vdn5a9hb-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e
