Hi,
"nollp" parameter defines if DW DMAC channel supports multi block
transfer or not.
It is calculated in runtime, but differently depending on on
availability of pdata. If pdata is absent "nollp" is calculated using
autoconfig hardware registers. Otherwise "nollp" is calculated using
the next
On Fri, 2016-08-12 at 13:59 +0300, Andy Shevchenko wrote:
> On Fri, 2016-08-12 at 08:03 +0000, Eugeniy Paltsev wrote:
> >
> > Hi,
> >
> > "nollp" parameter defines if DW DMAC channel supports multi block
> > transfer or not.
> >
> >
dmatest on ARC SDP with DW DMAC became broken after df5c7386
("dmaengine: dw: some Intel devices has no memcpy support") and
30cb2639 ("dmaengine: dw: don't override platform data with autocfg")
commits.
* After df5c7386 commit "DMA_MEMCPY" capability option doesn't
get set correctly in platform
Hi,
Not every time. For example, last time I debug mmap3 LTP's test, which
stuck in "D" state, I didn't recieve any messages until I enabled this
option. This happends on nsim 700.
On Thu, 2016-07-21 at 09:17 -0700, Vineet Gupta wrote:
> On 07/21/2016 07:52 AM, Eugeniy
On Mon, 2016-08-15 at 15:41 +0300, Andy Shevchenko wrote:
> On Mon, 2016-08-15 at 11:10 +0000, Eugeniy Paltsev wrote:
> >
> > On Fri, 2016-08-12 at 17:08 +0300, Andy Shevchenko wrote:
> > >
> > >
> > > >
> > > > >
> > > >
.
This leads to inoperability of DW DMAC.
This patch adds reading missed parameters from device tree.
Note there's a prerequisite http://www.spinics.net/lists/dmaengine/msg10682.html
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 6 ++
1 file
fixies according to previous RFC
* Add DT bindings
Eugeniy Paltsev (2):
dt-bindings: Document the Synopsys DW AXI DMA bindings
dmaengine: Add DW AXI DMAC driver
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 33 +
drivers/dma/Kconfig|8 +
drivers/dma
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/K
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++
1 file changed, 34 insertions(+)
creat
Thanks for response.
My comments are given inline below.
On Wed, 2017-01-25 at 19:25 +0200, Andy Shevchenko wrote:
> On Wed, 2017-01-25 at 18:34 +0300, Eugeniy Paltsev wrote:
> >
> > This patch adds support for the DW AXI DMAC controller.
> >
> > DW AXI DMAC is a p
Hi Andy,
thanks for respond.
I'm agree with most of the comments.
My comments below.
On Fri, 2017-01-20 at 15:38 +0200, Andy Shevchenko wrote:
> On Fri, 2017-01-20 at 13:50 +0300, Eugeniy Paltsev wrote:
> >
> > This patch adds support for the DW AXI DMAC controller.
>
On Fri, 2016-08-19 at 17:39 +0300, Andy Shevchenko wrote:
> On Tue, 2016-08-16 at 14:31 +0300, Eugeniy Paltsev wrote:
> >
> > DW DMAC on ARC SDP became broken after df5c7386 ("dmaengine: dw:
> > some
> > Intel
> > devices has no memcpy support") and 3
Commit 0d4cb44da6ca0e8 ("dmaengine: dmatest: Add support for
scatter-gather DMA mode") changes default "dmatest" behavior by
changing default mode from "memcpy" to "scatter-gather".
Now "memcpy" gets back as default mode.
Signed-off-by: Eugeniy P
or autoconfig registers)
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/core.c| 31 +++---
drivers/dma/dw/platform.c| 42 +---
include/linux/platform_data/dma-dw.h | 20 +++---
Hi Andy,
what do you think about these changes?
On Thu, 2016-09-15 at 16:14 +0300, Eugeniy Paltsev wrote:
> This patch is to address a proposal by Andy in this thread:
> http://www.spinics.net/lists/dmaengine/msg10754.html
> Split platform data to actual hardware properties, and platform
t;1" for ARM.
I am wondering, if it was done for any special reason?
Otherwise, set max ULP for "cos (M_PI_6l * 2.0) == 0.5" test to
"1" instead of "0" for ARC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
test/math/libm-test-ulps-arc |
or autoconfig registers)
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes for v2:
- use separate bool values for quirks in "dw_dma_platform_data" instead of
common bit field.
- convert device tree properties reading to unified device property API.
I
Convert device tree properties reading to unified device
property API, update properties names as ordered by DT policy.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 33 ++---
1 file changed, 14 insertions(
Split platform data to actual hardware properties, and platform quirks.
Now we able to use quirks and hardware properties separately from
different sources (pdata, device tree or autoconfig registers)
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/
Add "DW_DMA_IS_LLP_SUPPORTED" flag. Use this flag to get rid
of "dwc->nollp" as separate variable.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/core.c | 11 ++-
drivers/dma/dw/regs.h | 2 +-
2 files changed, 7 insertions(+
On Tue, 2016-11-08 at 15:36 +0200, Andy Shevchenko wrote:
> On Tue, 2016-11-08 at 12:22 +0000, Eugeniy Paltsev wrote:
> >
> > On Mon, 2016-11-07 at 15:55 +0200, Andy Shevchenko wrote:
>
> >
> > >
> > > >
> > > > + * @only_quirks_used:
C PGU driver to be able work with drm bridge hdmi encoder
interface. The hdmi connector code isn't needed anymore as we expect
the adv7511 bridge driver to create/manage the connector.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes for v2:
- re
Hi Andy,
On Fri, 2016-10-07 at 14:05 +0300, Andy Shevchenko wrote:
> On Wed, 2016-10-05 at 15:14 +0000, Eugeniy Paltsev wrote:
> >
> > Hi Andy,
> > what do you think about these changes?
> I was off for few weeks, will look at this next week.
>
I was wondering yo
On Thu, 2016-10-20 at 13:48 +0300, Andy Shevchenko wrote:
> On Thu, 2016-09-15 at 16:14 +0300, Eugeniy Paltsev wrote:
> >
> > This patch is to address a proposal by Andy in this thread:
> > http://www.spinics.net/lists/dmaengine/msg10754.html
> > Split platform data to
C PGU driver to be able work with drm bridge hdmi encoder
interface. The hdmi connector code isn't needed anymore as we expect
the adv7511 bridge driver to create/manage the connector.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/gpu/drm/arc/arcpgu_hdmi.c | 144
Move adding DT property and adding documentation for this
property to one patch.
Eugeniy Paltsev (2):
DW DMAC: enable memory-to-memory transfers support
DW DMAC: add multi-block property to device tree
Documentation/devicetree/bindings/dma/snps-dma.txt | 2 ++
arch/arc/boot/dts/abilis_tb10x.
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Acked-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
dr
multi block transfers (if present) via DT.
Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.
Acked-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@syn
multi block transfers (if present) via DT.
Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Also:
Update DT documentation.
Update existing pl
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Acked-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
dr
ory transfers.
So we don't need to read it from DT. So enable it by default,
if we read configuration from DT.
* Use "multi-block" instead of "hw-llp" name to be more clear.
* Move adding DT property and adding documentation for this
property to one patch.
Eugeniy Pa
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Acked-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
dr
it by default,
if we read configuration from DT.
* Use "multi-block" instead of "hw-llp" name to be more clear.
* Move adding DT property and adding documentation for this
property to one patch.
Eugeniy Paltsev (2):
DW DMAC: enable memory-to-memory transfers support
D
block transfers (if present) via DT.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/core.c| 2 +-
drivers/dma/dw/platform.c| 5 +
include/linux/platform_data/dma-dw.h | 4 ++--
3 files changed, 8 insertions(+), 3 deletions(-)
support via DT.
Fix white spaces.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Documentation/devicetree/bindings/dma/snps-dma.txt | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt
b/Documen
Memory-to-memory dma transfers were disabled by default if we
used DT to cofigure DMAC.
Add is-memcpu property, so it became possible to enable
memory-to-memory transfers support via DT.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 3 +++
Rename is_private to is-private as ordered by DT policy.
The change leaves the support for the old format.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/dw/platform.c b/drivers/
Hi Andy,
On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote:
> Overall, since we are going to expose some properties to the Device
> Tree
> I would really think twice about naming. Better if we reuse something
> existing already.
>
> So, what I can see is
>
> dmacap,private
>
multi block transfers (if present) via DT.
Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.
Update DT documentation.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Documentation/devi
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 6 ++
1 file changed, 6 insertions(+)
diff
e don't need to read it from DT. So enable it by default,
if we read configuration from DT.
* Use "multi-block" instead of "hw-llp" name to be more clear.
* Move adding DT property and adding documentation for this
property to one patch.
Eugeniy Paltsev (2):
DW DMAC: e
multi block transfers (if present) via DT.
Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.
Update DT documentation.
Update existing platform data.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/dw/platform.c | 6 ++
1 file changed, 6 insertions(+)
diff
Hi Andy,
Could you possibly tell me your ideas about these changes?
Thanks.
On Fri, 2016-10-28 at 18:59 +0300, Eugeniy Paltsev wrote:
> This series is to address a proposal by Andy in these threads:
> http://www.spinics.net/lists/dmaengine/msg11506.html
> http://www.spinics.net/lists/
Hi Vinod!
Thanks for respond.
My comments below.
On Tue, 2017-03-14 at 08:30 +0530, Vinod Koul wrote:
> On Tue, Feb 21, 2017 at 11:38:04PM +0300, Eugeniy Paltsev wrote:
>
> > +static void vchan_desc_put(struct virt_dma_desc *vdesc)
> > +{
> > + axi_desc_
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of upcoming development board from Synopsys.
In this driver implementation only DMA_MEMCPY and DMA_SG transfers
are supported.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/dma/K
itch to virt-dma API (according to previous RFC)
* Small fixies according to previous RFC
* Add DT bindings
Eugeniy Paltsev (2):
dt-bindings: Document the Synopsys DW AXI DMA bindings
dmaengine: Add DW AXI DMAC driver
.../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 +
Hi,
On Fri, 2017-04-21 at 18:13 +0300, Andy Shevchenko wrote:
> On Fri, 2017-04-21 at 14:29 +0000, Eugeniy Paltsev wrote:
> > On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote:
> > > On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:
> > > > This pat
ud field of earlycon device structure by baud value
from device tree or from options (if they exist) when we use
of_setup_earlycon
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/tty/serial/earlycon.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drive
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
odkin <abrod...@synopsys.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v8 -> v9:
* Revert removing of ARC_PLAT_HSDK (now it is called ARC_SOC_HSDK)
as it breaks uniprocessor configuation build.
* Enable INPUT_EVDEV in hsdk_defconfig as it is required for
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
I'll add this to
[PATCH 3/3 v9] ARC: hsdk: initial port for HSDK board
On Tue, 2017-08-15 at 20:12 +0300, Alexey Brodkin wrote:
> This is required for user-space apps to work with keyboard/mice.
>
> Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
> Cc: Eug
Hi Rob,
On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> On Tue, Aug 15, 2017 at 12:21 PM, Eugeniy Paltsev
> <eugeniy.palt...@synopsys.com> wrote:
> > [snip]
> > @@ -282,7 +283,15 @@ int __init of_setup_earlycon(const struc
On Wed, 2017-08-16 at 08:46 -0500, Rob Herring wrote:
> On Wed, Aug 16, 2017 at 6:52 AM, Eugeniy Paltsev
> <eugeniy.palt...@synopsys.com> wrote:
> > Hi Rob,
> >
> > On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> > > On Tue, Aug 15, 2017 at 12:21
On Fri, 2017-08-11 at 15:46 +0200, Philipp Zabel wrote:
> Hi Eugeniy,
>
> On Thu, 2017-08-10 at 19:41 +0300, Eugeniy Paltsev wrote:
> > ARC AXS10x boards support custom IP-block which allows to control
> > reset signals of selected peripherals. For example DW GMAC,
for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
* Remove all MODULE* defines as this driver can't be build
Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
in device tree.
We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
clock source (same pll in our case).
We override cpus node in skeleton as we don't need this change for
nsim.
Signed-off
Use cpu's node "cpu-freq" param instead of platform-specific
"/cpu_card/core_clk" as it works only if we use fixed-clock for cpu
clocking.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 12
1 file c
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/axc003.dtsi | 11 +--
ar
On Thu, 2017-08-17 at 11:11 +, Eugeniy Paltsev wrote:
> Hi Alexandru,
>
> On Wed, 2017-08-16 at 15:15 -0700, Alexandru Gagniuc wrote:
> > This is split into the SOC bindings, and the board dts. The Endor
> > board is currently an FPGA emulation. Once real, silicon arr
rsion
> + */
> +
> +/* This skeleton is based on the ARC700 CPU */
> +#include "skeleton.dtsi"
Perhaps it is better not to use skeleton.dtsi as we are planning to
get rid of it.
--
Eugeniy Paltsev
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
>
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
Note that PAE remapping for DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Eug
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../bindings/clock/snps,hsdkv1-pll-clock.txt | 28 ++
MAINT
; load again [reset happens])
Also some reset controllers have only reset callback instead of
assert + deassert callbacks pair, so handle this case.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 -
1 file cha
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
.../bindings/reset/snps,hsdk-v1-reset.txt | 28
MAINT
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
- Remove defines of the unused registers.
Hi Philipp,
On Wed, 2017-07-19 at 17:07 +0200, Philipp Zabel wrote:
> On Tue, 2017-07-18 at 20:25 +0300, Eugeniy Paltsev wrote:
> > The HSDK v1 periphery IPs can be reset by accessing some registers
> > from the CGU block.
> >
> > The list of available reset li
ate a node for each core interrupt controller because
we wouldn't able to specify which one is parent for interrupt
distribution unit:
>>>-
cpus {
cpu@0 { intc@0 };
cpu@1 { intc@1 };
};
interrupt-distribution-unit {
interrupt-parent =
};
&
"sp" register is member of "scratch" structure (which is nested
in user_regs_struct)
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
linux/arc/arch_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux/arc/arch_regs.c b/l
On Wed, 2017-06-21 at 22:16 +0300, Eugeniy Paltsev wrote:
Hi Stephen, Michael,
Maybe you have any comments or remarks about this patch? And if you
don't could you please apply it.
Thanks a lot!
> AXS10X boards manages it's clocks using various PLLs. These PLL has
> same
>
On Tue, 2017-04-25 at 21:12 +0300, Andy Shevchenko wrote:
> On Tue, 2017-04-25 at 15:16 +0000, Eugeniy Paltsev wrote:
> > On Mon, 2017-04-24 at 19:56 +0300, Andy Shevchenko wrote:
> > > On Mon, 2017-04-24 at 15:55 +0000, Eugeniy Paltsev wrote:
> > > > Hi,
> > &
On Wed, 2017-04-26 at 18:04 +0300, Andy Shevchenko wrote:
> On Tue, 2017-04-25 at 21:12 +0300, Andy Shevchenko wrote:
> > On Tue, 2017-04-25 at 15:16 +, Eugeniy Paltsev wrote:
> > > On Mon, 2017-04-24 at 19:56 +0300, Andy Shevchenko wrote:
> > > > On Mon, 2017
we can use DMA_CTRL_REUSE flag for all channel types.
Also it allows to test reusing mechanism with simply mem-to-mem dma
test.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
include/linux/dmaengine.h | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff
y uart device via "console" parameter in
bootargs:
-->8
chosen {
bootargs = "console=ttyS1"
stdout-path =
};
serial0: uart0@... {}
serial1: uart1@... {} /* serial1 is used as console (ttyS1) */
-
On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Add core pll node (core_clk) to manage cpu frequency.
> > core_clk represents pll itself.
> > input_clk represents clock signal source (basically xtal) which
&
On Tue, 2017-08-22 at 14:40 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
> > in device tree.
> >
> > We add "cpu-freq" only to cpu 0 as all cpus ar
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
Signed-off-by: Vlad Zakharov <vzak...@synopsys.com>
Signed-off-by: Jose Abreu <joab...@synopsys.com>
---
Changes for v4:
- fix resource freing after error in of_axs10x_pll_clk_setup
- add axs10x* prefix to main functions a
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
m code.
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Documentation/devicetree/bindings/arc/hsdk.txt | 7 ++
arch/arc/Kconfig | 1 +
arch/arc/Makefile |
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++
On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So def
after reset.
As of today only the following lines are used:
- DW GMAC - line 5
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v1 -> v2:
* The creg reset register is self-clearing so we don't need to clear it
manually. Fixed it.
* Use reset callbac
DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v2 -> v3:
* Remove v1 suffix as we finaly got rid of v1 suffix in reset
Increase SDIO CIU frequency from 1250Hz to 5000Hz by
switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
NOTE: This patch can possibly fi
On Thu, 2017-10-05 at 06:04 -0700, Vineet Gupta wrote:
> Hi Eugeniy,
>
> On 09/22/2017 09:49 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on HSDK hangs sometimes after SW reset, so
> > add reset node to make possible to reset DW ethernet controller HW.
> >
On Wed, 2017-09-06 at 12:54 -0700, Vineet Gupta wrote:
> On 09/06/2017 11:21 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on AXS10x hangs sometimes after SW reset, so
> > add temporary quirk to reset DW ethernet controller IP core.
> > This quirk can be removed afte
1
to 1250 Hz until we fix dw sdio driver itself.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/hsdk.dts | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 8
Hi Petr,
On Tue, 2017-09-05 at 16:54 +0200, Petr Mladek wrote:
> On Mon 2017-08-28 19:58:07, Eugeniy Paltsev wrote:
> > In the current implementation we take the first console that
> > registers if we didn't select one.
> >
> > But if we specify console via "stdo
/9903375/)
will be available in upstream.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/plat-axs10x/axs10x.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index f1ac679..cf14ebc 100644
--- a/ar
-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_m
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