RE: [PATCH v3 03/18] clocksource: Add NPS400 timers driver

From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] Sent: Friday, December 04, 2015 11:13 AM >It would be cleaner to define a fixed clock and then add a phandle in the DT. > timer_clk: timer_clk { > #clock-cells = <0>; > compatible = "fixed-clock"; >

Re: [PATCH v3 01/18] Documentation: Add EZchip vendor to binding list

>From: Daniel Lezcano >Sent: Friday, December 4, 2015 10:07 AM >> >> diff --git a/Documentation/devicetree/bindings/arc/eznps.txt >> b/Documentation/devicetree/bindings/arc/eznps.txt >> new file mode 100644 >> index 000..f8b5e9b >> --- /dev/null >> +++

Re: [PATCH v3 03/18] clocksource: Add NPS400 timers driver

>From: Daniel Lezcano >Sent: Friday, December 4, 2015 11:13 AM >> +obj-$(CONFIG_ARC_PLAT_EZNPS) += timer-nps.o >CONFIG_CLKSRC_NPS I wish this driver to be build only for this specific ARC platform. This clock source is embedded in our SoC. It is not meant to be built

RE: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips

From: Marc Zyngier [mailto:marc.zyng...@arm.com] Sent: Thursday, December 03, 2015 8:34 PM >>> Silly question: why cannot you just write the actual instruction >>> instead of shoving the instruction like this? Also, .inst would be >>> more appropria

RE: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips

From: Marc Zyngier [mailto:marc.zyng...@arm.com] Sent: Wednesday, December 16, 2015 11:31 AM >> +static int __init nps400_of_init(struct device_node *node, >> + struct device_node *parent) >> +{ >> +if (parent) >> +panic("DeviceTree incore ic not a

[PATCH v4 02/19] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> --- include/soc/nps/com

[PATCH v4 14/19] ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg

From: Noam Camus <no...@ezchip.com> We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus <no...@ezchip.com> --- arch/arc/include/asm/atom

[PATCH v4 07/19] ARC: rwlock: disable interrupts in !LLSC variant

From: Noam Camus <no...@ezchip.com> If we hold rwlock and interrupt occures we may end up spinning on it for ever during softirq. Note that this lock is an internal lock and since the lock is free to be used from any context, the lock needs to be IRQ-safe. Below you may see an e

Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ()

>From: Vineet Gupta >Sent: Wednesday, December 30, 2015 12:10 PM >> --- a/arch/arc/Kconfig >> +++ b/arch/arc/Kconfig >> @@ -32,6 +32,7 @@ config ARC >> select HAVE_OPROFILE >> select HAVE_PERF_EVENTS >> select IRQ_DOMAIN >> + select

[PATCH v5 20/20] ARC: Add eznps platform to Kconfig and Makefile

From: Noam Camus <no...@ezchip.com> This commit should be left last since only now eznps platform is in state which one can actually use. Signed-off-by: Noam Camus <no...@ezchip.com> --- arch/arc/Kconfig |1 + arch/arc/Makefile |5 + 2 files changed, 6 insertions(+),

Re: [PATCH v5 04/20] clocksource: Add NPS400 timers driver

.4-rc6 next-20151223] >url: >https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-plat-eznps-to-ARC/20151227-220433 >base: https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next >config: i386-allmodconfig (attached as .config) >reproduce: > #

[PATCH v5 00/20] Adding plat-eznps to ARC

From: Noam Camus <no...@ezchip.com> v5: 1) irqchip -- work with handle_domain_irq(), and remove use of irq_set_default_host() 2) clocksource -- initialize clockevents as well by parsing interrupts node of DT 3) Do not use IPI with irq generic infrastructure v4: 1) irqchip

[PATCH v5 12/20] ARC: [plat-eznps] Add eznps board defconfig and dts

From: Noam Camus <no...@ezchip.com> Adding default configuration file and DTS file Signed-off-by: Noam Camus <no...@ezchip.com> --- arch/arc/boot/dts/eznps.dts| 94 arch/arc/configs/nps_defconfig | 85 +

RE: [PATCH V2 63/63] clocksources: Switch back to the clksrc table

imer", > -nps_timer_init); > +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", > +nps_timer_init); > diff --git a/drivers/clocksource/timer-oxnas-rps.c > b/drivers/clocksource/timer-oxnas-rps.c > index 0d99f

RE: Click source driver

>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] >Sent: Tuesday, June 28, 2016 11:32 AM >> I noticed that arc-timer driver appears twice in DTS file so first one >> will invoke initialization of clockevent and second the clocksource. >> Please note that both update same global variable

[PATCH v3 1/3] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> --- include/soc/nps/com

Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

>From: Daniel Lezcano >Sent: Tuesday, February 9, 2016 3:38 PM >Actually I was referring to clk_prepare_enable, clocksource_register_hz. >Agree clk_get_rate is always valid. Thanks for making this clear. Any way as you can see I do call pr_err() in case of error just

RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] >Sent: Wednesday, February 10, 2016 12:55 AM >> pr_err() in case of error just like most drivers around. By "hang" do >> you mean calling panic()? >No. I meant the errors are caught but no action is taken, the execution >continues

Re: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips

Hi Marc, Please respond to Vineet last email. I wish to close the IPI handling within my patch set. Regards, Noam From: Vineet Gupta <vineet.gup...@synopsys.com> Sent: Monday, January 25, 2016 3:08:34 PM To: Marc Zyngier; Noam Camus; linux-sn

[PATCH 2/2] irqchip: add nps Internal and external irqchips

From: Noam Camus <no...@ezchip.com> Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network d

[PATCH 1/2] clocksource: Add NPS400 timers driver

From: Noam Camus <no...@ezchip.com> Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus <no...@ezchip.com> Cc: Da

[PATCH 0/2] Adding NPS400 drivers

From: Noam Camus <no...@ezchip.com> General summay: Both drivers are now apart of previous basic patch set of new platform for ARC. The rest is now can be seen at ARC srctree: https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/ Now ARC is supporting DT for clockevents and the int

[PATCH v2 3/3] irqchip: add nps Internal and external irqchips

From: Noam Camus <no...@ezchip.com> Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network d

RE: Interesting csd deadlock on ARC

>From: Peter Zijlstra [mailto:pet...@infradead.org] >Sent: Tuesday, February 23, 2016 12:40 PM >The only requirement for irq_work is that it runs after the NMI completes and >runs from regular IRQ context. >There are no strict interrupt priority >requirements, only that it happens. We here

RE: [PATCH v5 0/3] Adding NPS400 drivers

Waiting for your feedback on my v5 patch set :) -Original Message- From: Noam Camus Sent: Thursday, February 11, 2016 8:41 PM To: linux-ker...@vger.kernel.org Cc: linux-snps-arc@lists.infradead.org; daniel.lezc...@linaro.org; marc.zyng...@arm.com; Chris Metcalf; Tal Zilcer; Gilad Ben

Re: [PATCH v5 3/3] irqchip: add nps Internal and external irqchips

Hi Jason, The patch set got change log, see cover letter that summarize all changes with respect to whole set. https://lkml.org/lkml/2016/2/11/609 Let me know if it works for you. Noam ___ linux-snps-arc mailing list

[PATCH v4 3/3] irqchip: add nps Internal and external irqchips

From: Noam Camus <no...@ezchip.com> Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network d

[PATCH v4 2/3] clocksource: Add NPS400 timers driver

From: Noam Camus <no...@ezchip.com> Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus <no...@ezchip.com> Cc: Da

[PATCH v4 1/3] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> --- include/soc/nps/com

[PATCH v4 0/3] Adding NPS400 drivers

From: Noam Camus <no...@ezchip.com> Change Log-- v4: clocksource -- Apply all Daniel comments (Thanks) Handle gracefull return and also using clocksoure mmio driver v3: irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource --

[PATCH v5 0/3] Adding NPS400 drivers

From: Noam Camus <no...@ezchip.com> Change Log-- v5: Clocksource, irqchip - Fix gracefull return. replace call to panic() with pr_err() and proper return value. v4: clocksource -- Apply all Daniel comments (Thanks) Handle gra

[PATCH v5 1/3] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> --- include/soc/nps/com

[PATCH v2 0/3] Adding NPS400 drivers

From: Noam Camus <no...@ezchip.com> Change Log-- v2: Add header file include/soc/nps/common.h. Now to build we do not depend on ARC subtree. General summay: Both drivers are now apart of previous basic patch set of new platform for ARC. The rest is now can be seen at ARC srctree:

Re: [PATCH v8 3/3] irqchip: add nps Internal and external irqchips

behalf of Noam Camus <noa...@mellanox.com> Sent: Sunday, April 3, 2016 9:14 PM To: daniel.lezc...@linaro.org; marc.zyng...@arm.com; ja...@lakedaemon.net Cc: Thomas Gleixner; linux-snps-arc@lists.infradead.org; Noam Camus; linux-ker...@vger.kernel.org Subject: [PATCH v8 3/3] irqchip: add

[PATCH v6 1/3] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> --- include/soc/nps/com

[PATCH v7 3/3] irqchip: add nps Internal and external irqchips

From: Noam Camus <no...@ezchip.com> Adding EZchip NPS400 support. Internal interrupts are handled by Multi Thread Manager (MTM) Once interrupt is serviced MTM is acked for deactivating the interrupt. External interrupts are handled by MTM as well as at Global Interrupt Controller (GI

[PATCH v7 2/3] clocksource: Add NPS400 timers driver

From: Noam Camus <no...@ezchip.com> Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus <no...@ezchip.com> Cc: Da

[PATCH v7 1/3] soc: Support for EZchip SoC

From: Noam Camus <no...@ezchip.com> This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus <no...@ezchip.com> Cc: Daniel Lezcano <daniel.lezc...

[PATCH] ARC: CONFIG_NODES_SHIFT fix default values

From: Noam Camus <noa...@mellanox.com> Seem like values assigned as absolute number and not and shift value, i.e. should be 0 for one node (2^0) and 1 for couple of nodes (2^1) Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/Kconfig |4 ++-- 1 files changed, 2 inse

[PATCH] ARC: [plat-eznps] add missing atomic_fetch_xxx operations

From: Noam Camus <noa...@mellanox.com> Build brekeage since last changes to generic atomic operations. Added couple of missing macros which are now mandatory Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/include/asm/atomic.h |2 ++ 1 files changed, 2 inse

RE: [PATCH v2] ARC: [plat-eznps] set default baud for early console

> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] > Sent: Tuesday, November 8, 2016 4:08 PM >Could you please provide a changelog (v1 -> v2) so reviewers may have a hint >about changes you made if any. ... Just fix some typos in log This line somehow was removed from patch while

[PATCH] ARC: [plat-eznps] remove IPI clear from SMP operations

From: Noam Camus <noa...@mellanox.com> Generic IRQ mechanism is already acknowledge the IPI IRQ. Doing this once more time in IPI handler is not needed. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/plat-eznps/smp.c |6 -- 1 files changed, 0 insertions(+),

RE: [PATCH] ARC: Adjust cpuinfo for non-continuous cpu ids

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] > Sent: Tuesday, October 18, 2016 8:49 PM >> >> num_possible_cpus() returns how many CPUs may be present on system. >> However we want the highest possible CPU number. > >Highest possible number "Detected" at boot ? Can you explain a bit

[PATCH v2] ARC: Adjust cpuinfo for non-continuous cpu ids

From: Noam Camus <no...@ezchip.com> num_possible_cpus() returns how many CPUs may be present on system. However we want the highest possible CPU number. This may be differ in a sparsed possible CPUs map. Such map achived by OF for plat-eznps. For example if we have: possible cpus ma

[PATCH] ARC: Adjust cpuinfo for non-continuous cpu ids

From: Noam Camus <no...@ezchip.com> num_possible_cpus() returns how many CPUs may be present on system. However we want the highest possible CPU number. This may be differ in a sparsed possible CPUs map. Signed-off-by: Noam Camus <no...@ezchip.com> Acked-by: Vineet Gupta <vgu.

[PATCH v8 3/3] clocksource: Add clockevent support to NPS400 driver

From: Noam Camus <noa...@mellanox.com> Till now we used clockevent from generic ARC driver. This was enough as long as we worked with simple multicore SoC. When we are working with multithread SoC each HW thread can be scheduled to receive timer interrupt using timer mask register. This

[RESEND PATCH v7 2/3] clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer

From: Noam Camus <noa...@mellanox.com> nps_setup_clocksource() should take node as only argument as defined by typedef int (*of_init_fn_1_ret)(struct device_node *) Therefore need to replace: int __init nps_setup_clocksource(struct device_node *node, struct clk *clk) with int

[RESEND PATCH v7 1/3] soc: Support for NPS HW scheduling

From: Noam Camus <noa...@mellanox.com> This new header file is for NPS400 SoC (part of ARC architecture). The header file includes macros for save/restore of HW scheduling. The control of HW scheduling is achieved by writing core registers. This code was moved from arc/plat-eznps so

RE: [PATCH 5/9] ARC: breakout aux handling into a seperate header

>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] >Sent: Tuesday, November 1, 2016 12:48 AM >ARC timers use aux registers for programming and this paves way for moving ARC >timer drivers into drivers/clocksource Maybe in this patch or just another one could you move from timer.c to the

[PATCH] ARC: Fix build for missing ATOMIC_INIT definition

From: Noam Camus <noa...@mellanox.com> Make ATOMIC_INIT available for all ARC platforms (including plat-eznps) Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/include/asm/atomic.h |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/arc

[PATCH 03/10] ARC: typo fix in mm/fault.c

From: Liav Rehana <li...@mellanox.com> Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/mm/fault.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fau

[PATCH 07/10] ARC: [plat-eznps] disabled stall counter due to a HW bug

From: Noam Camus <noa...@mellanox.com> This counter represents threshold for consecutive stall that which trigger HW threads scheduling. Low values of this counter cause downgrade in performance and in the worst case even a livelock. Signed-off-by: Noam Camus <noa...@mellanox.com> -

[PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

From: Noam Camus <noa...@mellanox.com> Due to a HW bug in NPS400 we get from time to time false TLB miss. Workaround this by validating each miss. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/mm/tlbex.S | 10 ++ 1 files changed, 10 insertions(+), 0 deleti

[PATCH 09/10] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

From: Noam Camus <noa...@mellanox.com> When HW threads are active we want CPU to enter idle state only for the calling HW thread and not to put on sleep all HW threads sharing this core. For this need the NPS400 got dedicated instruction so only calling thread is entring sleep and all

[PATCH 08/10] ARC: [plat-eznps] spinlock aware for MTM

From: Noam Camus <noa...@mellanox.com> This way when we execute "ex" during trying to hold lock we can switch to other HW thread and utilize the core intead of just spinning on a lock. We noticed about 10% improvement of execution time with hackbench test. Signed-off-by:

[PATCH 00/10] ARC plat-eznps upstream cont.

From: Noam Camus <noa...@mellanox.com> With this patch set I continue the effort of upstreaming the eznps platform for arch/arc. it combine of patches for typos and other for HW erratas and some for performance. All selected as ones that may be obvious for merge with arc next. This was

[PATCH 04/10] ARC: typos fix in kernel/entry-compact.S

From: Liav Rehana <li...@mellanox.com> Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/kernel/entry-compact.S | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arc

[PATCH 05/10] ARC: [plat-eznps] typo fix at Kconfig

From: Noam Camus <noa...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/plat-eznps/Kconfig |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig index 1595a38..feaa471 10064

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

From: Noam Camus <noa...@mellanox.com> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR. If set, it will cause the kernel to handle user memory error as a machine check exception. It is required in order to align the NPS simulator memory error handling to the one of the NPS400 rea

[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

From: Noam Camus <noa...@mellanox.com> This way when we execute "ex" during trying to hold lock we can switch to other HW thread and utilize the core intead of just spinning on a lock. We noticed about 10% improvement of execution time with hackbench test. Signed-off-by:

[PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level

From: Noam Camus <noa...@mellanox.com> The reasons are: 1) speeding up boot time, becomes critical for many CPUs machine, e.g. NPS400 with 4K CPUs 2) shorten kernel log at boot time, again easy to scan for large scale machines such NPS400 Signed-off-by: Noam Camus <noa...@mel

[PATCH v2 03/11] ARC: typo fix in mm/fault.c

From: Liav Rehana <li...@mellanox.com> Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> Reviewed-by: Alexey Brodkin <abrod...@synopsys.com> --- arch/arc/mm/fault.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

[PATCH v2 04/11] ARC: typos fix in kernel/entry-compact.S

From: Liav Rehana <li...@mellanox.com> Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> Reviewed-by: Alexey Brodkin <abrod...@synopsys.com> --- arch/arc/kernel/entry-compact.S | 22 +++--- 1 files chang

[PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata

From: Noam Camus <noa...@mellanox.com> Due to a HW bug in NPS400 we get from time to time false TLB miss. Workaround this by validating each miss. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/mm/tlbex.S |9 + 1 files changed, 9 insertions(+), 0 deleti

[PATCH v2 09/11] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

From: Noam Camus <noa...@mellanox.com> When HW threads are active we want CPU to enter idle state only for the calling HW thread and not to put on sleep all HW threads sharing this core. For this need the NPS400 got dedicated instruction so only calling thread is entring sleep and all

[PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig

From: Noam Camus <noa...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> Reviewed-by: Alexey Brodkin <abrod...@synopsys.com> --- arch/arc/plat-eznps/Kconfig |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/plat-eznps/Kconfig b/a

RE: [PATCH 07/10] ARC: [plat-eznps] disabled stall counter due to a HW bug

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] >Sent: Thursday, May 25, 2017 14:10 PM ... >> diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c >> index ffd..e0cb36b 100644 >> --- a/arch/arc/plat-eznps/mtm.c >> +++ b/arch/arc/plat-eznps/mtm.c >> @@ -119,8 +119,6

RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] > Sent: Thursday, May 25, 2017 14:15 PM >> >> diff --git a/arch/arc/kernel/entry-compact.S >> b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644 >> --- a/arch/arc/kernel/entry-compact.S >> +++

RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] >Sent: Thursday, May 25, 2017 14:31 PM ... >> > Why don't you just make simulator behaving exactly as your real chip? >> I can't change simulator core behavior. nSIM is a Synopsys proprietary code. >Well probably it worth discussing with

RE: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] >Sent: Thursday, May 25, 2017 14:01 PM ... >>  /* Get free TLB slot: Set = computed from vaddr, way = random */ >>  sr  TLBGetIndex, [ARC_REG_TLBCOMMAND] >>   >> @@ -287,6 +294,9 @@ ex_saved_reg1: >>  #else >>  sr

RE: [PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] > Sent: Friday, June 2, 2017 21:36 PM ... >> arch/arc/include/asm/spinlock.h |6 ++ >> 1 files changed, 6 insertions(+), 0 deletions(-) >> >> diff --git a/arch/arc/include/asm/spinlock.h >> b/arch/arc/include/asm/spinlock.h

RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] > Sent: Friday, June 2, 2017 22:04 PM >> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig >> index feaa471..c5f946c 100644 >> --- a/arch/arc/plat-eznps/Kconfig >> +++ b/arch/arc/plat-eznps/Kconfig >> @@ -32,3 +32,14

RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

> From: Noam Camus > Sent: Wednesday, June 7, 2017 9:08 AM >To: 'Vineet Gupta' <vineet.gup...@synopsys.com>; >linux-snps-arc@lists.infradead.org >Cc: linux-ker...@vger.kernel.org; Elad Kanfi <elad...@mellanox.com> >Subject: RE: [PATCH v2 11/11] ARC: [p

[PATCH 05/11] ARC: Support more than one PGDIR for KVADDR

From: Noam Camus <noa...@mellanox.com> This way FIXMAP can have 2 PTEs per CPU even for NR_CPUS=4096 For the extreme case like in eznps platform We use all gutter between kernel and user. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/Kconfig

[PATCH 04/11] ARC: Add CPU topology

From: Noam Camus <noa...@mellanox.com> Now it is used for NPS SoC for multi-core of 256 cores and SMT of 16 HW threads per core. This way with topology the scheduler is much efficient in creating domains and later using them. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch

[PATCH 01/11] ARC: set level of log per CPU during boot to be debug level

From: Noam Camus <noa...@mellanox.com> The reasons are: 1) speeding up boot time, becomes critical for many CPUs machine, e.g. NPS400 with 4K CPUs 2) shorten kernel log at boot time, again easy to scan for large scale machines such NPS400 Signed-off-by: Noam Camus <noa...@mel

[PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register

hanged afterwards. Signed-off-by: Elad Kanfi <elad...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/plat-eznps/include/plat/ctop.h |1 + arch/arc/plat-eznps/mtm.c | 12 2 files changed, 13 insertions(+), 0 deletions(-) diff --g

[PATCH 00/11] plat-eznps upstream cont. set 2

From: Noam Camus <noa...@mellanox.com> With this patch set I continue the effort of upstreaming the eznps platform for arch/arc. It comprise of couple of patches from last set yet not accepted, patches for HW erratas and some misc extensions such for HIGHMEM / NUMA. This set got more g

[PATCH 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers

From: Noam Camus <no...@ezchip.com> thread_struct got new field for data plane of eznps platform. This field got place for data plane auxiliary registers and for any extra registers that might be changed in kernel code. We save EFLAGS, and GPA1 auxiliary registers since they may be c

[PATCH 10/11] ARC: [plat-eznps] handle dedicated AUX registers

parent value. Signed-off-by: Noam Camus <no...@ezchip.com> --- arch/arc/include/asm/entry-compact.h | 24 arch/arc/include/asm/ptrace.h|5 + arch/arc/kernel/process.c|4 3 files changed, 33 insertions(+), 0 deletions(-) diff

[PATCH 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

From: Noam Camus <noa...@mellanox.com> We add ability for all cores at NPS SoC to control the number of cycles HW thread can execute before it is replace with another eligible HW thread within the same core. The replacement is done by the HE scheduler. Signed-off-by: Noam Camu

[PATCH 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

thread in each core. On platforms that implement a different set of auxiliary registers there is a need to initialize them on every cpu and not just the for the first thread of the core. Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- a

[PATCH v2 06/12] ARC: Support more than one PGDIR for KVADDR

From: Noam Camus <noa...@mellanox.com> This way FIXMAP can have 2 PTEs per CPU even for NR_CPUS=4096 For the extreme case like in eznps platform We use all gutter between kernel and user. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/Kconfig

[PATCH v2 05/12] ARC: Add CPU topology

From: Noam Camus <noa...@mellanox.com> Now it is used for NPS SoC for multi-core of 256 cores and SMT of 16 HW threads per core. This way with topology the scheduler is much efficient in creating domains and later using them. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch

[PATCH v2 08/12] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

From: Noam Camus <noa...@mellanox.com> We add ability for all cores at NPS SoC to control the number of cycles HW thread can execute before it is replace with another eligible HW thread within the same core. The replacement is done by the HE scheduler. Signed-off-by: Noam Camu

[PATCH v2 12/12] ARC: [plat-eznps] avoid toggling of DPC register

hanged afterwards. Signed-off-by: Elad Kanfi <elad...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/plat-eznps/include/plat/ctop.h |1 + arch/arc/plat-eznps/mtm.c | 12 2 files changed, 13 insertions(+), 0 deletions(-) diff --g

[PATCH v2 01/12] ARC: [plat-eznps] Handle memory error as an exception

From: Noam Camus <noa...@mellanox.com> On ARC700, user mode memory error is treated as L2 interrupt, but NPS hardware treats it as Machine Check exception. Address this by defining an NPS specific bus error handler. Signed-off-by: Noam Camus <noa...@mellanox.com> Signed-off-by: Elad

[PATCH v2 10/12] ARC: [plat-eznps] Save/Restore extra auxiliary registers

From: Noam Camus <no...@ezchip.com> thread_struct got new field for data plane of eznps platform. This field got place for data plane auxiliary registers and for any extra registers that might be changed in kernel code. We save EFLAGS, and GPA1 auxiliary registers since they may be c

[PATCH v2 02/12] ARC: set level of log per CPU during boot to be debug level

From: Noam Camus <noa...@mellanox.com> The reasons are: 1) speeding up boot time, becomes critical for many CPUs machine, e.g. NPS400 with 4K CPUs 2) shorten kernel log at boot time, again easy to scan for large scale machines such NPS400 Signed-off-by: Noam Camus <noa...@mel

[PATCH v2 03/12] ARC: send ipi to all cpus sharing task mm in case of page fault

From: Noam Camus <noa...@mellanox.com> This patch is derived due to performance issue. The use case is a page fault that resides on more than the local cpu. Trying to broadcast all CPUs results on performance degradation. So we try to avoid this by sending only to the relevant CPUs. Sign

[PATCH v2 09/12] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

thread in each core. On platforms that implement a different set of auxiliary registers there is a need to initialize them on every cpu and not just the for the first thread of the core. Signed-off-by: Liav Rehana <li...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- a

[PATCH v2 07/12] ARC: [NUMA] added CONFIG_NUMA for plat-eznps

From: Noam Camus <noa...@mellanox.com> This is needed for NPS400 where high memory is assigned to node1 where the associated addresses are lower than node0. This use case is not typical and just using discontigmem is not enough since nodes assumed to have increasing address range. i.e. a

[PATCH v3 05/11] ARC: Support more than one PGDIR for KVADDR

From: Noam Camus <noa...@mellanox.com> This way FIXMAP can have 2 PTEs per CPU even for NR_CPUS=4096 For the extreme case like in eznps platform We use all gutter between kernel and user. Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/Kconfig

[PATCH v3 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

From: Noam Camus <noa...@mellanox.com> This patch is derived due to performance issue. The use case is a page fault that resides on more than the local cpu. Trying to broadcast all CPUs results on performance degradation. So we try to avoid this by sending only to the relevant CPUs. Sign

[PATCH v3 06/11] ARC: [NUMA] added CONFIG_NUMA for plat-eznps

From: Noam Camus <noa...@mellanox.com> This is needed for NPS400 where high memory is assigned to node1 where the associated addresses are lower than node0. This use case is not typical and just using discontigmem is not enough since nodes assumed to have increasing address range. i.e. a

[PATCH v3 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers

From: Noam Camus <no...@ezchip.com> thread_struct got new field for data plane of eznps platform. This field got place for data plane auxiliary registers and for any extra registers that might be changed in kernel code. We save EFLAGS, and GPA1 auxiliary registers since they may be c

[PATCH v3 00/11] plat-eznps upstream cont. set 2

From: Noam Camus <noa...@mellanox.com> Change Log: V2 -> V3 1) turn ARC prink's into pr_info as suggested by Vineet 2) For new command line argument (hs counter) shorten error massage to a single line, again as Vineet commented. V1 -> V2 1) I added "Handle memory error as an

[PATCH v3 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

From: Noam Camus <noa...@mellanox.com> We add ability for all cores at NPS SoC to control the number of cycles HW thread can execute before it is replace with another eligible HW thread within the same core. The replacement is done by the HW scheduler. Signed-off-by: Noam Camu

[PATCH v3 01/11] ARC: set level of log per CPU during boot to be info level

From: Noam Camus <noa...@mellanox.com> Now it can be hidden by passing higher loglevel sevirity at cmdline The reasons are: 1) speeding up boot time, becomes critical for many CPUs machine, e.g. NPS400 with 4K CPUs 2) shorten kernel log at boot time, again easy to scan for large

[PATCH v3 11/11] ARC: [plat-eznps] avoid toggling of DPC register

hanged afterwards. Signed-off-by: Elad Kanfi <elad...@mellanox.com> Signed-off-by: Noam Camus <noa...@mellanox.com> --- arch/arc/plat-eznps/include/plat/ctop.h |1 + arch/arc/plat-eznps/mtm.c | 12 2 files changed, 13 insertions(+), 0 deletions(-) diff --g

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