from:"Vineet Gupta"

Re: [PATCH v2] ARC: Fix typos

2024-03-29 Thread Vineet Gupta

On 3/29/24 15:14, Bjorn Helgaas wrote:
> From: Bjorn Helgaas 
>
> Fix typos, most reported by "codespell arch/arc".  Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas 

Added to ARC for-curr.


Thx,
-Vineet

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Re: [PATCH 2/8] ARC: Fix typos

2024-03-29 Thread Vineet Gupta




On 1/4/24 11:02, Bjorn Helgaas wrote:
>>> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
>>> index 0b3bb529d246..5414d9f5c40c 100644
>>> --- a/arch/arc/kernel/signal.c
>>> +++ b/arch/arc/kernel/signal.c
>>> @@ -9,7 +9,7 @@
>>>   * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
>>>   *  -do_signal() supports TIF_RESTORE_SIGMASK
>>>   *  -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
>>> - *  -sys_rt_sigsuspend() now comes from generic code, so discard arch 
>>> implemen
>>> + *  -sys_rt_sigsuspend() now comes from generic code, so discard arch 
>>> implement
>>   
> Thanks again.
>
> Added these and a couple other ones to my local copy in case there's a
> v2:

Sorry this slipped thru cracks. I don't see it upstream and given some
pending fixes for Linus can pick this up.
So I take v1 + the fixlet below or do you have any more local changes
and prefer respin/resending ?

Thx,
-Vineet

>
> diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h 
> b/arch/arc/include/asm/pgtable-bits-arcv2.h
> index f8f85c04d7a8..8ebec1b21d24 100644
> --- a/arch/arc/include/asm/pgtable-bits-arcv2.h
> +++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
> @@ -66,7 +66,7 @@
>   * Other rules which cause the divergence from 1:1 mapping
>   *
>   *  1. Although ARC700 can do exclusive execute/write protection (meaning R
> - * can be tracked independent of X/W unlike some other CPUs), still to
> + * can be tracked independently of X/W unlike some other CPUs), still to
>   * keep things consistent with other archs:
>   *  -Write implies Read:   W => R
>   *  -Execute implies Read: X => R
> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
> index 5414d9f5c40c..3490d005e6d4 100644
> --- a/arch/arc/kernel/signal.c
> +++ b/arch/arc/kernel/signal.c
> @@ -8,15 +8,16 @@
>   *
>   * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
>   *  -do_signal() supports TIF_RESTORE_SIGMASK
> - *  -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
> - *  -sys_rt_sigsuspend() now comes from generic code, so discard arch 
> implement
> + *  -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
> + *  -sys_rt_sigsuspend() now comes from generic code, so discard arch
> + *   implementation
>   *  -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
>   *  -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and 
> leaves
>   *   the job to do_signal()
>   *
>   * vineetg: July 2009
>   *  -Modified Code to support the uClibc provided userland sigreturn stub
> - *   to avoid kernel synthesing it on user stack at runtime, costing TLB
> + *   to avoid kernel synthesizing it on user stack at runtime, costing TLB
>   *   probes and Cache line flushes.
>   *
>   * vineetg: July 2009


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Re: recent kernel warning

2024-03-28 Thread Vineet Gupta



On 3/28/24 11:01, Alexey Brodkin wrote:
> Hi Vineet,
>
> Indeed, it's incorrect placement of "#interrupt-cells" in the Ethernet
> controller node.
> I'll remove it and will send out a patch with the fix.

And while at it please audit all the DTs in arch/arc

Thx,
-Vineet

>
> Thanks for the pointer.
>
> -Alexey
> --------
> *From:* Vineet Gupta 
> *Sent:* Thursday, March 28, 2024 5:15 AM
> *To:* Alexey Brodkin ; arcml
> 
> *Subject:* recent kernel warning
>  
> Alexey,
>
> Can you have someone look at the following kernel warning:
>
>   DTC arch/arc/boot/dts/hsdk.dtb
> ../arch/arc/boot/dts/hsdk.dts:207.23-235.5: Warning
> (interrupt_provider): /soc/ethernet@8000: '#interrupt-cells' found, but
> node is not an interrupt provider
> arch/arc/boot/dts/hsdk.dtb: Warning (interrupt_map): Failed prerequisite
> 'interrupt_provider'
>
> Thx,
> -Vineet


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Re: [PATCH 2/2] ARC: mm: fix new code about cache aliasing

2024-03-28 Thread Vineet Gupta




On 3/28/24 06:57, Mathieu Desnoyers wrote:
> On 2024-03-28 01:39, Vineet Gupta wrote:
>> Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() 
>> across all architectures")
>>
>> Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
>> at least).
>>
>> Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
>> PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
>> cache is not relevant to ARC anymore.
>>
>> P.S. : This has been discussed a few times on lists [1]
>> P.S.2: Please CC the arch maintainers and/or mailing list before adding
>> such interfaces.
> Because 8690bbcf3b70 was introducing a tree-wide change affecting all
> architectures, I CC'd linux-a...@vger.kernel.org. I expected all
> architecture maintainers to follow that list, which is relatively
> low volume.

Ideally yeah arch maintainers should be lurking there.


> I'm sorry that you learn about this after the fact as a result.

Please don't be, no harm done, the fix was easy ;-)

> My intent was to use the list rather than CC about 50 additional
> people/mailing lists.

That is true but I don't think maintainers mind that in general. I still
posit that any new interfaces to arch code should be explicitly run by them.

> Of course, if VIPT aliasing is removed from ARC, removing the
> config ARCH_HAS_CPU_CACHE_ALIASING and using the generic
> cpu_dcache_is_aliasing() is the way to go. Feel free to add
> my:
>
> Acked-by: Mathieu Desnoyers 

Thx,
-Vineet

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Re: next: arc: defconfig - gcc-9 - mmu-arcv2.h:82:2: error: implicit declaration of function 'write_aux_reg' [-Werror=implicit-function-declaration]

2024-03-27 Thread Vineet Gupta




On 3/25/24 23:39, Naresh Kamboju wrote:
> The following arc defconfig build warnings / errors noticed on today's
> Linux next-20240326 tag.
>
> Regressions:
> * arc - defconfig - gcc-9 build failed.
>
> Reported-by: Linux Kernel Functional Testing 
>
> Build log:
> -
> arch/arc/kernel/ptrace.c:342:16: warning: no previous prototype for
> 'syscall_trace_enter' [-Wmissing-prototypes]
>   342 | asmlinkage int syscall_trace_enter(struct pt_regs *regs)
>   |^~~
> arch/arc/kernel/kprobes.c:193:15: warning: no previous prototype for
> 'arc_kprobe_handler' [-Wmissing-prototypes]
>   193 | int __kprobes arc_kprobe_handler(unsigned long addr, struct
> pt_regs *regs)
>   |   ^~
> In file included from arch/arc/include/asm/mmu.h:21,
>  from arch/arc/include/asm/pgtable.h:14,
>  from include/linux/pgtable.h:6,
>  from include/asm-generic/io.h:1047,
>  from arch/arc/include/asm/io.h:232,
>  from include/linux/io.h:13,
>  from kernel/dma/coherent.c:6:
> arch/arc/include/asm/mmu-arcv2.h: In function 'mmu_setup_asid':
> arch/arc/include/asm/mmu-arcv2.h:82:2: error: implicit declaration of
> function 'write_aux_reg' [-Werror=implicit-function-declaration]
>82 |  write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
>   |  ^
> cc1: some warnings being treated as errors

Thx for the report. Fix posted for first 2 warnings [1]

I can't reproduce the last warning about write_aux_reg() despite using
the config from 3rd link below.

-Vineet

[1]
http://lists.infradead.org/pipermail/linux-snps-arc/2024-March/007916.html


>
> Steps to reproduce:
> ---
> # tuxmake --runtime podman --target-arch arc --toolchain gcc-9
> --kconfig defconfig
>
>
> Links:
>  - 
> https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20240325/testrun/23149630/suite/build/test/gcc-9-defconfig/log
>  - 
> https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20240325/testrun/23149630/suite/build/test/gcc-9-defconfig/history/
>  - 
> https://storage.tuxsuite.com/public/linaro/lkft/builds/2eA2VSZdDsL0DMBBhjoauN9IVoK/
>
> --
> Linaro LKFT
> https://lkft.linaro.org


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[PATCH 1/2] ARC: Fix -Wmissing-prototypes warnings

2024-03-27 Thread Vineet Gupta

| ../arch/arc/kernel/kprobes.c:193:15: warning: no previous prototype for 
'arc_kprobe_handler' [-Wmissing-prototypes]
|  193 | int __kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs 
*regs)
|
|../arch/arc/kernel/ptrace.c:342:16: warning: no previous prototype for 
'syscall_trace_enter' [-Wmissing-prototypes]
|  342 | asmlinkage int syscall_trace_enter(struct pt_regs *regs)

Link: 
https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20240325/testrun/23149630/suite/build/test/gcc-9-defconfig/log
Reported-by: Linux Kernel Functional Testing 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/ptrace.h | 2 +-
 arch/arc/kernel/kprobes.c | 7 ---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 00b9318e551e..cf79df0b2570 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -169,7 +169,7 @@ static inline unsigned long regs_get_register(struct 
pt_regs *regs,
return *(unsigned long *)((unsigned long)regs + offset);
 }
 
-extern int syscall_trace_entry(struct pt_regs *);
+extern int syscall_trace_enter(struct pt_regs *);
 extern void syscall_trace_exit(struct pt_regs *);
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arc/kernel/kprobes.c b/arch/arc/kernel/kprobes.c
index e71d64119d71..f8e2960832d9 100644
--- a/arch/arc/kernel/kprobes.c
+++ b/arch/arc/kernel/kprobes.c
@@ -190,7 +190,8 @@ static void __kprobes setup_singlestep(struct kprobe *p, 
struct pt_regs *regs)
}
 }
 
-int __kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
+static int
+__kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
 {
struct kprobe *p;
struct kprobe_ctlblk *kcb;
@@ -241,8 +242,8 @@ int __kprobes arc_kprobe_handler(unsigned long addr, struct 
pt_regs *regs)
return 0;
 }
 
-static int __kprobes arc_post_kprobe_handler(unsigned long addr,
-struct pt_regs *regs)
+static int
+__kprobes arc_post_kprobe_handler(unsigned long addr, struct pt_regs *regs)
 {
struct kprobe *cur = kprobe_running();
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-- 
2.34.1


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[PATCH 0/2] ARC minor fixes

2024-03-27 Thread Vineet Gupta

Some fixlets for ARC.

Vineet Gupta (2):
  ARC: Fix -Wmissing-prototypes warnings
  ARC: mm: fix new code about cache aliasing

 arch/arc/Kconfig | 1 -
 arch/arc/include/asm/cachetype.h | 9 -
 arch/arc/include/asm/ptrace.h| 2 +-
 arch/arc/kernel/kprobes.c| 7 ---
 4 files changed, 5 insertions(+), 14 deletions(-)
 delete mode 100644 arch/arc/include/asm/cachetype.h

-- 
2.34.1


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[PATCH 2/2] ARC: mm: fix new code about cache aliasing

2024-03-27 Thread Vineet Gupta

Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() 
across all architectures")

Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).

Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.

P.S. : This has been discussed a few times on lists [1]
P.S.2: Please CC the arch maintainers and/or mailing list before adding
   such interfaces.

[1] 
http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html

Cc: Mathieu Desnoyers 
Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig | 1 -
 arch/arc/include/asm/cachetype.h | 9 -
 2 files changed, 10 deletions(-)
 delete mode 100644 arch/arc/include/asm/cachetype.h

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 99d2845f3feb..4092bec198be 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,7 +6,6 @@
 config ARC
def_bool y
select ARC_TIMERS
-   select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT
diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
deleted file mode 100644
index 05fc7ed59712..
--- a/arch/arc/include/asm/cachetype.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARC_CACHETYPE_H
-#define __ASM_ARC_CACHETYPE_H
-
-#include 
-
-#define cpu_dcache_is_aliasing()   true
-
-#endif
-- 
2.34.1


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recent kernel warning

2024-03-27 Thread Vineet Gupta

Alexey,

Can you have someone look at the following kernel warning:

  DTC arch/arc/boot/dts/hsdk.dtb
../arch/arc/boot/dts/hsdk.dts:207.23-235.5: Warning
(interrupt_provider): /soc/ethernet@8000: '#interrupt-cells' found, but
node is not an interrupt provider
arch/arc/boot/dts/hsdk.dtb: Warning (interrupt_map): Failed prerequisite
'interrupt_provider'

Thx,
-Vineet

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Re: [RFC v2.1 01/12] ARC: Use initializer for struct vm_unmapped_area_info

2024-03-01 Thread Vineet Gupta




On 3/1/24 16:17, Rick Edgecombe wrote:
> Future changes will need to add a new member to struct
> vm_unmapped_area_info. This would cause trouble for any call site that
> doesn't initialize the struct. Currently every caller sets each field
> manually, so if new fields are added they will be unitialized and the core
> code parsing the struct will see garbage in the new field.
>
> It could be possible to initialize the new field manually to 0 at each
> call site. This and a couple other options were discussed, and the
> consensus (see links) was that in general the best way to accomplish this
> would be via static initialization with designated field initiators.
> Having some struct vm_unmapped_area_info instances not zero initialized
> will put those sites at risk of feeding garbage into vm_unmapped_area() if
> the convention is to zero initialize the struct and any new field addition
> misses a call site that initializes each field manually.
>
> It could be possible to leave the code mostly untouched, and just change
> the line:
> struct vm_unmapped_area_info info
> to:
> struct vm_unmapped_area_info info = {};
>
> However, that would leave cleanup for the fields that are manually set
> to zero, as it would no longer be required.
>
> So to be reduce the chance of bugs via uninitialized fields, instead
> simply continue the process to initialize the struct this way tree wide.
> This will zero any unspecified members. Move the field initializers to the
> struct declaration when they are known at that time. Leave the fields out
> that were manually initialized to zero, as this would be redundant for
> designated initializers.
>
> Signed-off-by: Rick Edgecombe 
> Cc: Vineet Gupta 
> Cc: linux-snps-arc@lists.infradead.org
> Link: https://lore.kernel.org/lkml/202402280912.33AEE7A9CF@keescook/#t
> Link: 
> https://lore.kernel.org/lkml/j7bfvig3gew3qruouxrh7z7ehjjafrgkbcmg6tcghhfh3rhmzi@wzlcoecgy5rs/

LGTM.

Acked-by: Vineet Gupta 

Thx,
-Vineet

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Re: [PATCH bpf-next v1] ARC: Add eBPF JIT support

2024-02-13 Thread Vineet Gupta

+CC Bjorn

On 2/13/24 18:39, Alexei Starovoitov wrote:
> On Tue, Feb 13, 2024 at 5:20 AM Shahab Vahedi  wrote:
>> From: Shahab Vahedi 
>>
>> This will add eBPF JIT support to the 32-bit ARCv2 processors. The
>> implementation is qualified by running the BPF tests on a Synopsys HSDK
>> board with "ARC HS38 v2.1c at 500 MHz" as the 4-core CPU.
> ...
>> Signed-off-by: Shahab Vahedi 
>> ---
>>  Documentation/admin-guide/sysctl/net.rst |1 +
>>  Documentation/networking/filter.rst  |4 +-
>>  arch/arc/Kbuild  |1 +
>>  arch/arc/Kconfig |1 +
>>  arch/arc/net/Makefile|6 +
>>  arch/arc/net/bpf_jit.h   |  161 ++
>>  arch/arc/net/bpf_jit_arcv2.c | 3001 ++
>>  arch/arc/net/bpf_jit_core.c  | 1425 ++
>>  8 files changed, 4598 insertions(+), 2 deletions(-)
> This is pretty cool to see.
> I'm assuming this will get reviewed and will go through arc.git tree.

I'd be happy to take it via ARC tree and can review some of the arch
specific bits, but I'd hope BPF folks also review it critically.

Thx,
-Vineet

> Could you share performance numbers interpreter vs JITed ?


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[GIT PULL] ARC fixes for 6.7

2023-12-18 Thread Vineet Gupta

Hi Linus,

Late in the cycle but we have a bunch of fixes for ARC. Please pull.

Thx,
-Vineet

--->
The following changes since commit 33cc938e65a98f1d29d0a18403dbbee050dcad9a:

  Linux 6.7-rc4 (2023-12-03 18:52:56 +0900)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/
tags/arc-6.7-fixes

for you to fetch changes up to 9a733dc4fbeec3f6d99645b845712b035e7440cf:

  ARC: add hugetlb definitions (2023-12-13 19:33:10 -0800)


ARC fixes for 6.7

 - build error for hugetlb, sparse and smatch fixes

 - Removal of VIPT aliasing cache code


Pavel Kozlov (1):
  ARC: add hugetlb definitions

Vineet Gupta (5):
  ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper
  ARC: entry: move ARCompact specific bits out of entry.h
  ARC: mm: retire support for aliasing VIPT D$
  ARC: fix spare error
  ARC: fix smatch warning

 arch/arc/Kconfig |   5 --
 arch/arc/include/asm/cacheflush.h    |  43 ---
 arch/arc/include/asm/entry-arcv2.h   |  32 +
 arch/arc/include/asm/entry-compact.h |  87 +-
 arch/arc/include/asm/entry.h | 110 ++--
 arch/arc/include/asm/hugepage.h  |   7 ++
 arch/arc/include/asm/ptrace.h    |  14 ++--
 arch/arc/kernel/setup.c  |   4 +-
 arch/arc/kernel/signal.c |   6 +-
 arch/arc/mm/cache.c  | 136
++-
 arch/arc/mm/mmap.c   |  21 +-
 arch/arc/mm/tlb.c    |  16 ++---
 12 files changed, 155 insertions(+), 326 deletions(-)

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Re: [PATCH] ARC: add hugetlb definitions

2023-12-13 Thread Vineet Gupta




On 12/13/23 07:07, Pavel Kozlov wrote:
> From: Pavel Kozlov 
>
> Add hugetlb definitions if THP enabled. ARC doesn't support
> HugeTLB FS but it supports THP. Some kernel code such as pagemap
> uses hugetlb definitions with THP.
>
> This patch fixes ARC build issue (HPAGE_SIZE undeclared error) with
> TRANSPARENT_HUGEPAGE enabled.
>
> Signed-off-by: Pavel Kozlov 

Added to for-curr.

I'll pile this will rest of patches for some linux-next soaking.

Thx,
-Vineet

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Re: arch/arc/kernel/setup.c:203 arcv2_mumbojumbo() error: uninitialized symbol 'release'.

2023-12-08 Thread Vineet Gupta

On 11/27/23 22:22, Dan Carpenter wrote:
> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
> master
> head:   2cc14f52aeb78ce3f29677c2de1f06c0e91471ab
> commit: fad84e39f116035ae8d550c6020107b8ac113b45 ARC: boot log: eliminate 
> struct cpuinfo_arc #4: boot log per ISA
> config: arc-randconfig-r071-20231128 
> (https://download.01.org/0day-ci/archive/20231128/202311280906.vaiweaft-...@intel.com/config)
> compiler: arceb-elf-gcc (GCC) 13.2.0
> reproduce: 
> (https://download.01.org/0day-ci/archive/20231128/202311280906.vaiweaft-...@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version 
> of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot 
> | Reported-by: Dan Carpenter 
> | Closes: https://lore.kernel.org/r/202311280906.vaiweaft-...@intel.com/
>
> New smatch warnings:
> arch/arc/kernel/setup.c:203 arcv2_mumbojumbo() error: uninitialized symbol 
> 'release'.

Thx, I've posted a fix.

> Old smatch warnings:
> arch/arc/include/asm/thread_info.h:62 current_thread_info() error: 
> uninitialized symbol 'sp'.

This seems like a false warning. Its a register variable and thus can't
possibly be initialized.

static inline __attribute_const__ struct thread_info
*current_thread_info(void)
{
    register unsigned long sp asm("sp");
    return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
}

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[PATCH 2/5] ARC: entry: move ARCompact specific bits out of entry.h

2023-12-08 Thread Vineet Gupta

 - PUSHAUX/POPAUX helpers to ARCompact entry
 - use gas provided "push"/pop pseudo instructions

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/entry-compact.h | 55 ++-
 arch/arc/include/asm/entry.h | 66 
 2 files changed, 54 insertions(+), 67 deletions(-)

diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 9841f1186417..92c3e9f13252 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -33,6 +33,59 @@
 #include 
 #include/* For THREAD_SIZE */
 
+/* Note on the LD/ST addr modes with addr reg wback
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.areg1, [reg2, x]  => Pre Incr
+ *  Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *  Eff Addr for load = [reg2]
+ */
+
+.macro PUSHAX aux
+   lr  r9, [\aux]
+   pushr9
+.endm
+
+.macro POPAX aux
+   pop r9
+   sr  r9, [\aux]
+.endm
+
+.macro  SAVE_R0_TO_R12
+   pushr0
+   pushr1
+   pushr2
+   pushr3
+   pushr4
+   pushr5
+   pushr6
+   pushr7
+   pushr8
+   pushr9
+   pushr10
+   pushr11
+   pushr12
+.endm
+
+.macro RESTORE_R12_TO_R0
+   pop r12
+   pop r11
+   pop r10
+   pop r9
+   pop r8
+   pop r7
+   pop r6
+   pop r5
+   pop r4
+   pop r3
+   pop r2
+   pop r1
+   pop r0
+.endm
+
 .macro SAVE_ABI_CALLEE_REGS
pushr13
pushr14
@@ -267,7 +320,7 @@
SWITCH_TO_KERNEL_STK
 
 
-   PUSH0x003\LVL\()abcd/* Dummy ECR */
+   st.a0x003\LVL\()abcd, [sp, -4]  /* Dummy ECR */
sub sp, sp, 8   /* skip orig_r0 (not needed)
   skip pt_regs->sp, already saved above */
 
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index 8e4e40d2d54a..cf1ba376e992 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -21,72 +21,6 @@
 #include 
 #endif
 
-/* Note on the LD/ST addr modes with addr reg wback
- *
- * LD.a same as LD.aw
- *
- * LD.areg1, [reg2, x]  => Pre Incr
- *  Eff Addr for load = [reg2 + x]
- *
- * LD.ab   reg1, [reg2, x]  => Post Incr
- *  Eff Addr for load = [reg2]
- */
-
-.macro PUSH reg
-   st.a\reg, [sp, -4]
-.endm
-
-.macro PUSHAX aux
-   lr  r9, [\aux]
-   PUSHr9
-.endm
-
-.macro POP reg
-   ld.ab   \reg, [sp, 4]
-.endm
-
-.macro POPAX aux
-   POP r9
-   sr  r9, [\aux]
-.endm
-
-/*--
- * Helpers to save/restore Scratch Regs:
- * used by Interrupt/Exception Prologue/Epilogue
- *-*/
-.macro  SAVE_R0_TO_R12
-   PUSHr0
-   PUSHr1
-   PUSHr2
-   PUSHr3
-   PUSHr4
-   PUSHr5
-   PUSHr6
-   PUSHr7
-   PUSHr8
-   PUSHr9
-   PUSHr10
-   PUSHr11
-   PUSHr12
-.endm
-
-.macro RESTORE_R12_TO_R0
-   POP r12
-   POP r11
-   POP r10
-   POP r9
-   POP r8
-   POP r7
-   POP r6
-   POP r5
-   POP r4
-   POP r3
-   POP r2
-   POP r1
-   POP r0
-
-.endm
-
 /*
  * save user mode callee regs as struct callee_regs
  *  - needed by fork/do_signal/unaligned-access-emulation.
-- 
2.34.1


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[PATCH 5/5] ARC: fix smatch warning

2023-12-08 Thread Vineet Gupta

Reported-by: kernel test robot 
Reported-by: Dan Carpenter 
Closes: https://lore.kernel.org/r/202311280906.vaiweaft-...@intel.com/
Signed-off-by: Vineet Gupta 
---
 arch/arc/kernel/setup.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 4dcf8589b708..d08a5092c2b4 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -153,7 +153,7 @@ static int arcv2_mumbojumbo(int c, struct cpuinfo_arc 
*info, char *buf, int len)
 {
int n = 0;
 #ifdef CONFIG_ISA_ARCV2
-   const char *release, *cpu_nm, *isa_nm = "ARCv2";
+   const char *release = "", *cpu_nm = "HS38", *isa_nm = "ARCv2";
int dual_issue = 0, dual_enb = 0, mpy_opt, present;
int bpu_full, bpu_cache, bpu_pred, bpu_ret_stk;
char mpy_nm[16], lpb_nm[32];
@@ -172,8 +172,6 @@ static int arcv2_mumbojumbo(int c, struct cpuinfo_arc 
*info, char *buf, int len)
 * releases only update it.
 */
 
-   cpu_nm = "HS38";
-
if (info->arcver > 0x50 && info->arcver <= 0x53) {
release = arc_hs_rel[info->arcver - 0x51].str;
} else {
-- 
2.34.1


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[PATCH 3/5] ARC: mm: retire support for aliasing VIPT D$

2023-12-08 Thread Vineet Gupta

Legacy ARC700 processors (first generation of MMU enabled ARC cores) had
VIPT cached which could be configured such that they could alias.
Corresponding support in kernel (with all the obnoxious cache flush overhead)
was added in ARC port 10 years ago to support 1 silicon. That is long bygone
and we can let it RIP.

Cc: Matthew Wilcox (Oracle) 
Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig  |   5 --
 arch/arc/include/asm/cacheflush.h |  43 --
 arch/arc/mm/cache.c   | 136 ++
 arch/arc/mm/mmap.c|  21 +
 arch/arc/mm/tlb.c |  16 ++--
 5 files changed, 14 insertions(+), 207 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 3162db540ee9..1b0483c51cc1 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -49,7 +49,6 @@ config ARC
select OF
select OF_EARLY_FLATTREE
select PCI_SYSCALL if PCI
-   select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
select TRACE_IRQFLAGS_SUPPORT
 
@@ -232,10 +231,6 @@ config ARC_CACHE_PAGES
  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
  Global DISABLE + Per Page ENABLE won't work
 
-config ARC_CACHE_VIPT_ALIASING
-   bool "Support VIPT Aliasing D$"
-   depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
-
 endif #ARC_CACHE
 
 config ARC_HAS_ICCM
diff --git a/arch/arc/include/asm/cacheflush.h 
b/arch/arc/include/asm/cacheflush.h
index bd5b1a9a0544..563af3e75f01 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -44,31 +44,10 @@ void dma_cache_wback(phys_addr_t start, unsigned long sz);
 
 #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
 
-#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
-
 #define flush_cache_mm(mm) /* called on munmap/exit */
 #define flush_cache_range(mm, u_vstart, u_vend)
 #define flush_cache_page(vma, u_vaddr, pfn)/* PF handling/COW-break */
 
-#else  /* VIPT aliasing dcache */
-
-/* To clear out stale userspace mappings */
-void flush_cache_mm(struct mm_struct *mm);
-void flush_cache_range(struct vm_area_struct *vma,
-   unsigned long start,unsigned long end);
-void flush_cache_page(struct vm_area_struct *vma,
-   unsigned long user_addr, unsigned long page);
-
-/*
- * To make sure that userspace mapping is flushed to memory before
- * get_user_pages() uses a kernel mapping to access the page
- */
-#define ARCH_HAS_FLUSH_ANON_PAGE
-void flush_anon_page(struct vm_area_struct *vma,
-   struct page *page, unsigned long u_vaddr);
-
-#endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
-
 /*
  * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
  * This works around some PIO based drivers which don't call flush_dcache_page
@@ -76,28 +55,6 @@ void flush_anon_page(struct vm_area_struct *vma,
  */
 #define PG_dc_cleanPG_arch_1
 
-#define CACHE_COLORS_NUM   4
-#define CACHE_COLORS_MSK   (CACHE_COLORS_NUM - 1)
-#define CACHE_COLOR(addr)  (((unsigned long)(addr) >> (PAGE_SHIFT)) & 
CACHE_COLORS_MSK)
-
-/*
- * Simple wrapper over config option
- * Bootup code ensures that hardware matches kernel configuration
- */
-static inline int cache_is_vipt_aliasing(void)
-{
-   return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
-}
-
-/*
- * checks if two addresses (after page aligning) index into same cache set
- */
-#define addr_not_cache_congruent(addr1, addr2) \
-({ \
-   cache_is_vipt_aliasing() ?  \
-   (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0; \
-})
-
 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 do {   \
memcpy(dst, src, len);  \
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index f7e05c146637..9106ceac323c 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -145,10 +145,9 @@ int arc_cache_mumbojumbo(int c, char *buf, int len)
p_dc->sz_k = 1 << (dbcr.sz - 1);
 
n += scnprintf(buf + n, len - n,
-   "D-Cache\t\t: %uK, %dway/set, %uB Line, %s%s%s\n",
+   "D-Cache\t\t: %uK, %dway/set, %uB Line, %s%s\n",
p_dc->sz_k, assoc, p_dc->line_len,
vipt ? "VIPT" : "PIPT",
-   p_dc->colors > 1 ? " aliasing" : "",
IS_USED_CFG(CONFIG_ARC_HAS_DCACHE));
 
 slc_chk:
@@ -703,51 +702,10 @@ static inline void arc_slc_enable(void)
  * Exported APIs
  */
 
-/*
- * Handle cache congruency of kernel and userspace mappings of page

[PATCH 0/5] ARC updates

2023-12-08 Thread Vineet Gupta

Hi,

A pile of accrued changes, compile tested only.
Please test.

Thx,
-Vineet

Vineet Gupta (5):
  ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper
  ARC: entry: move ARCompact specific bits out of entry.h
  ARC: mm: retire support for aliasing VIPT D$
  ARC: fix spare error
  ARC: fix smatch warning

 arch/arc/Kconfig |   5 -
 arch/arc/include/asm/cacheflush.h|  43 -
 arch/arc/include/asm/entry-arcv2.h   |  32 +++
 arch/arc/include/asm/entry-compact.h |  87 -
 arch/arc/include/asm/entry.h | 110 +-
 arch/arc/include/asm/ptrace.h|  14 +--
 arch/arc/kernel/setup.c  |   4 +-
 arch/arc/kernel/signal.c |   6 +-
 arch/arc/mm/cache.c  | 136 ++-
 arch/arc/mm/mmap.c   |  21 +
 arch/arc/mm/tlb.c|  16 +---
 11 files changed, 148 insertions(+), 326 deletions(-)

-- 
2.34.1


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[PATCH 4/5] ARC: fix spare error

2023-12-08 Thread Vineet Gupta

Reported-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202312082320.vdn5a9hb-...@intel.com/
Signed-off-by: Vineet Gupta 
---
 arch/arc/kernel/signal.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index 0b3bb529d246..8f6f4a542964 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -62,7 +62,7 @@ struct rt_sigframe {
unsigned int sigret_magic;
 };
 
-static int save_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
+static int save_arcv2_regs(struct sigcontext __user *mctx, struct pt_regs 
*regs)
 {
int err = 0;
 #ifndef CONFIG_ISA_ARCOMPACT
@@ -75,12 +75,12 @@ static int save_arcv2_regs(struct sigcontext *mctx, struct 
pt_regs *regs)
 #else
v2abi.r58 = v2abi.r59 = 0;
 #endif
-   err = __copy_to_user(>v2abi, , sizeof(v2abi));
+   err = __copy_to_user(>v2abi, (void const *), sizeof(v2abi));
 #endif
return err;
 }
 
-static int restore_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
+static int restore_arcv2_regs(struct sigcontext __user *mctx, struct pt_regs 
*regs)
 {
int err = 0;
 #ifndef CONFIG_ISA_ARCOMPACT
-- 
2.34.1


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[PATCH 1/5] ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper

2023-12-08 Thread Vineet Gupta

And for ARcompact variant replace the PUSH/POP macros with gas provided
push/pop pseudo-instructions

This allows ISA specific implementation

e.g. Current ARCv2 PUSH/POP could be replaced with STD/LDL to save 2
registers at a time (w/o bothering with SP update each time) or
perhaps use ENTER_S/LEAVE_S to reduce code size

For ARCv3 ABI changed so callee regs are now r14-r26 (vs. r13-r25)
thus would need a different implementation.

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/entry-arcv2.h   | 32 
 arch/arc/include/asm/entry-compact.h | 32 
 arch/arc/include/asm/entry.h | 44 +++-
 arch/arc/include/asm/ptrace.h| 14 +
 4 files changed, 76 insertions(+), 46 deletions(-)

diff --git a/arch/arc/include/asm/entry-arcv2.h 
b/arch/arc/include/asm/entry-arcv2.h
index 4d13320e0c1b..3802a2daaf86 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -291,4 +291,36 @@
/* M = 8-1  N = 8 */
 .endm
 
+.macro SAVE_ABI_CALLEE_REGS
+   pushr13
+   pushr14
+   pushr15
+   pushr16
+   pushr17
+   pushr18
+   pushr19
+   pushr20
+   pushr21
+   pushr22
+   pushr23
+   pushr24
+   pushr25
+.endm
+
+.macro RESTORE_ABI_CALLEE_REGS
+   pop r25
+   pop r24
+   pop r23
+   pop r22
+   pop r21
+   pop r20
+   pop r19
+   pop r18
+   pop r17
+   pop r16
+   pop r15
+   pop r14
+   pop r13
+.endm
+
 #endif
diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index a0e760eb35a8..9841f1186417 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -33,6 +33,38 @@
 #include 
 #include/* For THREAD_SIZE */
 
+.macro SAVE_ABI_CALLEE_REGS
+   pushr13
+   pushr14
+   pushr15
+   pushr16
+   pushr17
+   pushr18
+   pushr19
+   pushr20
+   pushr21
+   pushr22
+   pushr23
+   pushr24
+   pushr25
+.endm
+
+.macro RESTORE_ABI_CALLEE_REGS
+   pop r25
+   pop r24
+   pop r23
+   pop r22
+   pop r21
+   pop r20
+   pop r19
+   pop r18
+   pop r17
+   pop r16
+   pop r15
+   pop r14
+   pop r13
+.endm
+
 /*--
  * Switch to Kernel Mode stack if SP points to User Mode stack
  *
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index 49c2e090cb5c..8e4e40d2d54a 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -87,48 +87,12 @@
 
 .endm
 
-/*--
- * Helpers to save/restore callee-saved regs:
- * used by several macros below
- *-*/
-.macro SAVE_R13_TO_R25
-   PUSHr13
-   PUSHr14
-   PUSHr15
-   PUSHr16
-   PUSHr17
-   PUSHr18
-   PUSHr19
-   PUSHr20
-   PUSHr21
-   PUSHr22
-   PUSHr23
-   PUSHr24
-   PUSHr25
-.endm
-
-.macro RESTORE_R25_TO_R13
-   POP r25
-   POP r24
-   POP r23
-   POP r22
-   POP r21
-   POP r20
-   POP r19
-   POP r18
-   POP r17
-   POP r16
-   POP r15
-   POP r14
-   POP r13
-.endm
-
 /*
  * save user mode callee regs as struct callee_regs
  *  - needed by fork/do_signal/unaligned-access-emulation.
  */
 .macro SAVE_CALLEE_SAVED_USER
-   SAVE_R13_TO_R25
+   SAVE_ABI_CALLEE_REGS
 .endm
 
 /*
@@ -136,18 +100,18 @@
  *  - could have been changed by ptrace tracer or unaligned-access fixup
  */
 .macro RESTORE_CALLEE_SAVED_USER
-   RESTORE_R25_TO_R13
+   RESTORE_ABI_CALLEE_REGS
 .endm
 
 /*
  * save/restore kernel mode callee regs at the time of context switch
  */
 .macro SAVE_CALLEE_SAVED_KERNEL
-   SAVE_R13_TO_R25
+   SAVE_ABI_CALLEE_REGS
 .endm
 
 .macro RESTORE_CALLEE_SAVED_KERNEL
-   RESTORE_R25_TO_R13
+   RESTORE_ABI_CALLEE_REGS
 .endm
 
 /*--
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 4a2b30fb5a98..00b9318e551e 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -54,6 +54,10 @@ struct pt_regs {
ecr_reg ecr;
 };
 
+struct callee_regs {
+   unsigned long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, 
r14, r13;
+};
+
 #define MAX_REG_OFFSET offsetof(struct pt_regs, ecr)
 
 #else
@@ -92,16 +96,14 @@ struct pt_regs {
unsigned long status32;
 };
 
-#define

Re: [PATCH 3/3] locking/atomic: openrisc: use generic_cmpxchg[64]_local for arch_cmpxchg[64]_local

2023-11-01 Thread Vineet Gupta





On 10/29/23 20:41, wuqiang.matt wrote:


arch_cmpxchg_relaxed:
...
  switch(sizeof((_p_))) {
  case 4:


arch_cmpxchg:
...
BUILD_BUG_ON(sizeof(_p_) != 4);
...

_p is the address pointer, so I'm thinking it's a typo but I couldn't
yet confirm. There is not much about arc processors in the web :(
Hmm, indeed. This seems like a bug but it depends on the 'llock  %0, 
[%1]'

can take a 32bit address or 32bit data register. Usually it should
check the size of data, but need to check with ISA manual.

Vineet, can you check this suspicious bug?


ARCv2 is a 32-bit ISA and LLOCK/SCOND work on 32-bit data.
So the pointers will be 32-bit anyways. Is the issue that 
pointer/cmpxchg operation could be on a smaller data type ?


For ARCv2 with CONFIG_ARC_HAS_LLSC, better add the data size checking and
only permit 32bit data size. Even for 32-bit system, data should can be
64bit 'long long'.


Right, makes sense. Can you send a patch ?



And In the case that CONFIG_ARC_HAS_LLSC is undefined, in 
arch_cmpxchg: the
pointer size checking is unnecessary, since it's using spinlock 
internally:


Correct, I had the same thought.



https://elixir.bootlin.com/linux/v6.6-rc7/source/arch/arc/include/asm/cmpxchg.h#L60: 


BUILD_BUG_ON(sizeof(_p_) != 4);    \
    \
/*    \
 * spin lock/unlock provide the needed smp_mb() before/after    \
 */    \
atomic_ops_lock(__flags);    \
_prev_ = *_p_;    \
if (_prev_ == _o_)    \
    *_p_ = _n_;    \
atomic_ops_unlock(__flags);


Can you do that fix in same patch as well ?


Another question about the naming: arch_cmpxchg_relaxed() implemented if
CONFIG_ARC_HAS_LLSC is configured and arch_cmpxchg() defined for the 
rest.

Are there any reasons for difference names ?


Yes the atomics API consists of _relaxed, _acquire, _release and unadorned.
_relaxed is the most efficient, with rest having some extra barriers.
If arch provides _relaxed, generic code can create the rest - assuming 
arch hardware can support the relaxed ones.

That is true for LLSC.

However for !LLSC, spinlock versions already have full barriers due to 
spinlock, so relaxed variant doesn't make sense.




As I checked, Synopsys has released 64bit ARC processors (HS66/HS68), but
I don't know the status of Linux kernel support.


Yes there's an internal ARC64 port running but it is not ready for 
upstreaming yet.


-Vineet

Re: [PATCH 3/3] locking/atomic: openrisc: use generic_cmpxchg[64]_local for arch_cmpxchg[64]_local

2023-10-29 Thread Vineet Gupta

On 10/28/23 20:26, Masami Hiramatsu (Google) wrote:

On Sun, 29 Oct 2023 00:40:17 +0800
"wuqiang.matt" wrote:

On 2023/10/28 20:49, Masami Hiramatsu (Google) wrote:

Hi Wuqiang,

On Thu, 26 Oct 2023 19:05:51 +0800
"wuqiang.matt" wrote:

On 2023/10/26 16:46, Arnd Bergmann wrote:

On Thu, Oct 26, 2023, at 09:39, wuqiang.matt wrote:

arch_cmpxchg[64]_local() are not defined for openrisc. So implement
them with generci_cmpxchg[64]_local, advised by Masami Hiramatsu.

Closes:
https://lore.kernel.org/linux-trace-kernel/169824660459.24340.14614817132696360531.stgit@devnote2
Closes:
https://lore.kernel.org/oe-kbuild-all/202310241310.ir5uukog-...@intel.com

Signed-off-by: wuqiang.matt

I think on architectures that have actual atomics, you
generally want to define this to be the same as arch_cmpxchg()
rather than the generic version.

It depends on the relative cost of doing one atomic compared
to an irq-disable/enable pair, but everyone else went with
the former if they could. The exceptions are armv4/armv5,
sparc32 and parisc, which don't have a generic cmpxchg()
or similar operation.

Sure, better native than the generic. I'll try to collect more
insights before next move.

So I will temporally remove the last change (use arch_cmpxchg_local
in objpool) until these series are rewritten with arch native code,
so that the next release will not break the kernel build.

Ok, it's fine to me. Thank you.

But this must be fixed because arch_cmpxchg_local() is required
for each arch anyway.

Yes. I'm working on the new update for arc/openrisc/hexagon. It would
be better resolve this issue first, then consider the objpool update
of using arch_cmpxchg_local.

You could do the thing that sparc64 and xtensa do, which
use the native cmpxchg for supported word sizes but the
generic version for 1- and 2-byte swaps, but that has its
own set of problems if you end up doing operations on both
the entire word and a sub-unit of the same thing.

Thank you for pointing out this. I'll do some research on these
implementations.

arc also has the LL-SC instruction but depends on the core feature,
so I think we can use it.

Right. The arc processor does have the CONFIG_ARC_HAS_LLSC option, but
I doubt the correctness of arch_cmpxchg_relaxed and arch_cmpxchg:

arch_cmpxchg_relaxed:
...
switch(sizeof((_p_))) {
case 4:

arch_cmpxchg:
...
BUILD_BUG_ON(sizeof(_p_) != 4);
...

_p is the address pointer, so I'm thinking it's a typo but I couldn't
yet confirm. There is not much about arc processors in the web :(

Hmm, indeed. This seems like a bug but it depends on the 'llock %0, [%1]'
can take a 32bit address or 32bit data register. Usually it should
check the size of data, but need to check with ISA manual.

Vineet, can you check this suspicious bug?

ARCv2 is a 32-bit ISA and LLOCK/SCOND work on 32-bit data.
So the pointers will be 32-bit anyways. Is the issue that
pointer/cmpxchg operation could be on a smaller data type ?

-Vineet

[GIT PULL] ARC updates for v6.6-rc1

2023-09-04 Thread Vineet Gupta


Hi Linus,

Some ARC updates for the current cycle.
There could be a minor merge conflict in arch/arc/Kconfig.

Thx,
-Vineet
->
The following changes since commit 2ccdd1b13c591d306f0401d98dedc4bdcd02b421:

  Linux 6.5-rc6 (2023-08-13 11:29:55 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-6.6-rc1


for you to fetch changes up to c40cad3b0aa47d6d0995637178fb6607ac3d45c1:

  ARC: boot log: fix warning (2023-08-23 22:36:19 -0700)


ARC updates for v6.6

 -Wmissing-prototype warning fixes

 - Missing compiler barrier in relaxed atomics

 - some uaccess simplification, declutter

 - Removal of massive glocal struct cpuinfo_arc from bootlog code

 - __switch_to consolidation (removal of inline asm variant)

 - use GP to cache task pointer (vs. r25)

 - Miscll rework of entry code


Pavel Kozlov (1):
  ARC: atomics: Add compiler barrier to atomic operations...

Rob Herring (1):
  arc: Explicitly include correct DT includes

Vineet Gupta (22):
  ARC: -Wmissing-prototype warning fixes
  ARC: uaccess: remove arc specific out-of-line handles for -Os
  ARC: uaccess: use optimized generic 
__strnlen_user/__strncpy_from_user

  ARC: uaccess: elide unaliged handling if hardware supports
  ARCv2: memset: don't prefetch for len == 0 which happens a alot
  ARC: boot log: eliminate struct cpuinfo_arc #1: mm
  ARC: boot log: eliminate struct cpuinfo_arc #2: cache
  ARC: boot log: eliminate struct cpuinfo_arc #3: don't export
  ARC: boot log: eliminate struct cpuinfo_arc #4: boot log per ISA
  ARC: entry: use gp to cache task pointer (vs. r25)
  ARC: kernel stack: INIT_THREAD need not setup @init_stack in @ksp
  ARC: __switch_to: asm with dwarf ops (vs. inline asm)
  ARC: __switch_to: move ksp to thread_info from thread_struct
  ARC: entry: rework (non-functional)
  ARC: entry: ARcompact EV_ProtV to use r10 directly
  ARC: entry: EV_MachineCheck dont re-read ECR
  ARC: entry: Add more common chores to EXCEPTION_PROLOGUE
  ARC: entry: replace 8 byte OR with 4 byte BSET
  ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne
  ARCv2: entry: rearrange pt_regs slightly
  ARC: pt_regs: create seperate type for ecr
  ARC: boot log: fix warning

 arch/arc/Kconfig  |   8 +-
 arch/arc/Makefile |   6 +-
 arch/arc/include/asm/arcregs.h    |  99 +++---
 arch/arc/include/asm/atomic-llsc.h    |   6 +-
 arch/arc/include/asm/atomic64-arcv2.h |   6 +-
 arch/arc/include/asm/current.h    |   2 +-
 arch/arc/include/asm/dwarf.h  |  32 +-
 arch/arc/include/asm/entry-arcv2.h    |  66 ++--
 arch/arc/include/asm/entry-compact.h  |  50 ++-
 arch/arc/include/asm/entry.h  | 128 +++-
 arch/arc/include/asm/irq.h    |   1 +
 arch/arc/include/asm/mmu.h    |   2 +
 arch/arc/include/asm/processor.h  |   7 +-
 arch/arc/include/asm/ptrace.h |  65 ++--
 arch/arc/include/asm/setup.h  |   8 +-
 arch/arc/include/asm/smp.h    |   2 +
 arch/arc/include/asm/thread_info.h    |  10 +-
 arch/arc/include/asm/uaccess.h    |  21 +-
 arch/arc/kernel/Makefile  |   9 +-
 arch/arc/kernel/asm-offsets.c |  14 +-
 arch/arc/kernel/ctx_sw.c  | 112 ---
 arch/arc/kernel/ctx_sw_asm.S  |  76 ++---
 arch/arc/kernel/devtree.c |   1 +
 arch/arc/kernel/entry-arcv2.S |  15 -
 arch/arc/kernel/entry-compact.S   |  19 +-
 arch/arc/kernel/entry.S   |  70 ++---
 arch/arc/kernel/intc-arcv2.c  |   2 +-
 arch/arc/kernel/kgdb.c    |   2 +-
 arch/arc/kernel/mcip.c    |   2 -
 arch/arc/kernel/process.c |  17 +-
 arch/arc/kernel/ptrace.c  |   8 +-
 arch/arc/kernel/setup.c   | 563 
--

 arch/arc/kernel/signal.c  |   1 +
 arch/arc/kernel/smp.c |   7 +-
 arch/arc/kernel/stacktrace.c  |   1 +
 arch/arc/kernel/traps.c   |   5 +-
 arch/arc/kernel/troubleshoot.c    |  13 +-
 arch/arc/lib/memset-archs.S   |   3 +-
 arch/arc/mm/cache.c   | 179 ---
 arch/arc/mm/extable.c |  11 -
 arch/arc/mm/fault.c   |   7 +-
 arch/arc/mm/init.c    |   1 +
 arch/arc/mm/tlb.c |  99 +++---
 arch/arc/plat-axs10x/axs10x.c |   1 -
 44 files changed, 724 insertions(+), 1033 deletions(-)
 delete mode 100644 arch/arc/kernel/ctx_sw.c


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Re: [PATCH] arc: Explicitly include correct DT includes

2023-08-23 Thread Vineet Gupta





On 8/23/23 10:00, Rob Herring wrote:

On Fri, Jul 14, 2023 at 11:39:49AM -0600, Rob Herring wrote:

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring 
---
  arch/arc/plat-axs10x/axs10x.c | 1 -
  1 file changed, 1 deletion(-)

Ping!


Sorry this fell through cracks, added to for-curr now !

Thx,
-Vineet

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[PATCH v2 16/20] ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

2023-08-19 Thread Vineet Gupta

THe high level structure of most ARC exception handlers is
 1. save regfile with EXCEPTION_PROLOGUE
 2. setup r0: EFA (not part of pt_regs)
 3. setup r1: pointer to pt_regs (SP)
 4. drop down to pure kernel mode (from exception)
 5. call the Linux "C" handler

Remove the boiler plate code by moving #2, #3, #4 into #1.

The exceptions to most exceptions are syscall Trap and Machine check
which don't do some of above for various reasons, so call a newly
introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original
EXCEPTION_PROLOGUE)

Tested-by: Pavel Kozlov 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/entry-arcv2.h   | 12 +++-
 arch/arc/include/asm/entry-compact.h | 12 +++-
 arch/arc/kernel/entry-arcv2.S| 15 ---
 arch/arc/kernel/entry-compact.S  | 13 -
 arch/arc/kernel/entry.S  | 19 ++-
 5 files changed, 24 insertions(+), 47 deletions(-)

diff --git a/arch/arc/include/asm/entry-arcv2.h 
b/arch/arc/include/asm/entry-arcv2.h
index a38ed505b3de..11b48ab39154 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -75,7 +75,7 @@
 .endm
 
 /**/
-.macro EXCEPTION_PROLOGUE
+.macro EXCEPTION_PROLOGUE_KEEP_AE
 
; Before jumping to Exception Vector, hardware micro-ops did following:
;   1. SP auto-switched to kernel mode stack
@@ -104,6 +104,16 @@
; OUTPUT: r10 has ECR expected by EV_Trap
 .endm
 
+.macro EXCEPTION_PROLOGUE
+
+   EXCEPTION_PROLOGUE_KEEP_AE  ; return ECR in r10
+
+   lr  r0, [efa]
+   mov r1, sp
+
+   FAKE_RET_FROM_EXCPN ; clobbers r9
+.endm
+
 /*
  * This macro saves the registers manually which would normally be autosaved
  * by hardware on taken interrupts. It is used by
diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 4e2ae82779ed..a0e760eb35a8 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -140,7 +140,7 @@
  *
  * After this it is safe to call the "C" handlers
  *-*/
-.macro EXCEPTION_PROLOGUE
+.macro EXCEPTION_PROLOGUE_KEEP_AE
 
/* Need at least 1 reg to code the early exception prologue */
PROLOG_FREEUP_REG r9, @ex_saved_reg1
@@ -179,6 +179,16 @@
; OUTPUT: r10 has ECR expected by EV_Trap
 .endm
 
+.macro EXCEPTION_PROLOGUE
+
+   EXCEPTION_PROLOGUE_KEEP_AE  ; return ECR in r10
+
+   lr  r0, [efa]
+   mov r1, sp
+
+   FAKE_RET_FROM_EXCPN ; clobbers r9
+.endm
+
 /*--
  * Restore all registers used by system call or Exceptions
  * SP should always be pointing to the next free stack element
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index a7e6a2174187..2e49c81c8086 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -125,11 +125,6 @@ ENTRY(mem_service)
 
EXCEPTION_PROLOGUE
 
-   lr  r0, [efa]
-   mov r1, sp
-
-   FAKE_RET_FROM_EXCPN
-
bl  do_memory_error
b   ret_from_exception
 END(mem_service)
@@ -138,11 +133,6 @@ ENTRY(EV_Misaligned)
 
EXCEPTION_PROLOGUE
 
-   lr  r0, [efa]   ; Faulting Data address
-   mov r1, sp
-
-   FAKE_RET_FROM_EXCPN
-
SAVE_CALLEE_SAVED_USER
mov r2, sp  ; callee_regs
 
@@ -163,11 +153,6 @@ ENTRY(EV_TLBProtV)
 
EXCEPTION_PROLOGUE
 
-   lr  r0, [efa]   ; Faulting Data address
-   mov r1, sp  ; pt_regs
-
-   FAKE_RET_FROM_EXCPN
-
mov blink, ret_from_exception
b   do_page_fault
 
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 77f0090554c5..774c03cc1d1a 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -256,16 +256,6 @@ ENTRY(EV_TLBProtV)
 
EXCEPTION_PROLOGUE  ; ECR returned in r10
 
-   lr  r0, [efa]   ; Faulting Data address (not part of pt_regs saved 
above)
-
-   ; Exception auto-disables further Intr/exceptions.
-   ; Re-enable them by pretending to return from exception
-   ; (so rest of handler executes in pure K mode)
-
-   FAKE_RET_FROM_EXCPN
-
-   mov   r1, sp; Handle to pt_regs
-
;-- (5) Type of Protection Violation? --
;
; ProtV Hardware Exception is triggered for Access Faults of 2 types
@@ -301,9 +291,6 @@ END(EV_TLBProtV)
 ENTRY(call_do_page_fault)
 
EXCEPTION_PROLOGUE
-   lr  r0, [efa]   ; Faulting Data address
-   mov   r1, sp
-   FAKE_RET_FROM_EXCPN
 
mov blink, ret_from_exception
b  do_page_fault
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 46582fbebcf2.

Re: [PATCH 16/20] ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

2023-08-19 Thread Vineet Gupta


On 8/18/23 05:56, pavel.koz...@synopsys.com wrote:

Hi Vineet,


Subject: [PATCH 16/20] ARC: entry: Add more common chores to
 EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
  1. save regfile with EXCEPTION_PROLOGUE
  2. setup r0: EFA (not part of pt_regs)
  3. setup r1: pointer to pt_regs (SP)
  4. drop down to pure kernel mode (from exception)
  5. call the Linux "C" handler

Remove the boiler plate code by moving #2, #3, #4 into #1.

The exceptions to most exceptions are syscall Trap and Machine check
which don't do some of above for various reasons, so call a newly
introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original
EXCEPTION_PROLOGUE)

I'm observing the ARC700 (nSIM) system freeze after this patch.

...
f000.serial: ttyS0 at MMIO 0xf000 (irq = 24, base_baud = 3125000) is a 
16550A
printk: console [ttyS0] enabled
printk: console [ttyS0] enabled
printk: bootconsole [uart8250] disabled
printk: bootconsole [uart8250] disabled
NET: Registered PF_PACKET protocol family
NET: Registered PF_KEY protocol family
clk: Disabling unused clocks
Freeing unused kernel image (initmem) memory: 2856K
This architecture does not have kernel memory protection.
Run /init as init process


@@ -128,11 +123,6 @@ ENTRY(EV_PrivilegeV)

  EXCEPTION_PROLOGUE

-   lr  r0, [efa]
-   mov r1, sp
-
-   FAKE_RET_FROM_EXCPN
-
  bl  do_privilege_fault
  b   ret_from_exception

The same update is also required for the call_do_page_fault wrapper for 
ARcompact.


Indeed I missed that part.

-Vineet

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Re: [PATCH 20/20] ARC: pt_regs: create seperate type for ecr

2023-08-17 Thread Vineet Gupta




On 8/17/23 05:09, pavel.koz...@synopsys.com wrote:

Hi Vineet,

I'm testing your updates and ran into the same build issue reported by the build
robot.
http://lists.infradead.org/pipermail/linux-snps-arc/2023-August/007522.html


#define MAX_REG_OFFSET offsetof(struct pt_regs, event)

This change causes a build issue for ARC700, as the event field has been
removed and the MAX_REG_OFFSET macro hasn't been updated.


I've posted v2 for 3 patches. Please reapply/retest the whole series.

Thx,
-Vineet


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[PATCH v2 20/20] ARC: pt_regs: create seperate type for ecr

2023-08-17 Thread Vineet Gupta

Reduces duplication in each ISA specific pt_regs

Tested-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202308151342.roq9urvv-...@intel.com
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/ptrace.h  | 47 +-
 arch/arc/kernel/asm-offsets.c  |  2 +-
 arch/arc/kernel/kgdb.c |  2 +-
 arch/arc/kernel/ptrace.c   |  4 +--
 arch/arc/kernel/traps.c|  4 +--
 arch/arc/kernel/troubleshoot.c | 13 +-
 arch/arc/mm/fault.c|  6 ++---
 7 files changed, 33 insertions(+), 45 deletions(-)

diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 3a054b695f28..4a2b30fb5a98 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -12,6 +12,17 @@
 
 #ifndef __ASSEMBLY__
 
+typedef union {
+   struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+   unsigned long state:8, vec:8, cause:8, param:8;
+#else
+   unsigned long param:8, cause:8, vec:8, state:8;
+#endif
+   };
+   unsigned long full;
+} ecr_reg;
+
 /* THE pt_regs: Defines how regs are saved during entry into kernel */
 
 #ifdef CONFIG_ISA_ARCOMPACT
@@ -40,21 +51,10 @@ struct pt_regs {
 *  Last word used by Linux for extra state mgmt (syscall-restart)
 * For interrupts, use artificial ECR values to note current prio-level
 */
-   union {
-   struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-   unsigned long state:8, ecr_vec:8,
- ecr_cause:8, ecr_param:8;
-#else
-   unsigned long ecr_param:8, ecr_cause:8,
- ecr_vec:8, state:8;
-#endif
-   };
-   unsigned long event;
-   };
+   ecr_reg ecr;
 };
 
-#define MAX_REG_OFFSET offsetof(struct pt_regs, event)
+#define MAX_REG_OFFSET offsetof(struct pt_regs, ecr)
 
 #else
 
@@ -62,18 +62,7 @@ struct pt_regs {
 
unsigned long orig_r0;
 
-   union {
-   struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-   unsigned long state:8, ecr_vec:8,
- ecr_cause:8, ecr_param:8;
-#else
-   unsigned long ecr_param:8, ecr_cause:8,
- ecr_vec:8, state:8;
-#endif
-   };
-   unsigned long event;
-   };
+   ecr_reg ecr;/* Exception Cause Reg */
 
unsigned long bta;  /* erbta */
 
@@ -131,13 +120,13 @@ struct callee_regs {
 /* return 1 if PC in delay slot */
 #define delay_mode(regs) ((regs->status32 & STATUS_DE_MASK) == STATUS_DE_MASK)
 
-#define in_syscall(regs)((regs->ecr_vec == ECR_V_TRAP) && !regs->ecr_param)
-#define in_brkpt_trap(regs) ((regs->ecr_vec == ECR_V_TRAP) && regs->ecr_param)
+#define in_syscall(regs)((regs->ecr.vec == ECR_V_TRAP) && !regs->ecr.param)
+#define in_brkpt_trap(regs) ((regs->ecr.vec == ECR_V_TRAP) && regs->ecr.param)
 
 #define STATE_SCALL_RESTARTED  0x01
 
-#define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED)
-#define syscall_restartable(reg) !(reg->state &  STATE_SCALL_RESTARTED)
+#define syscall_wont_restart(regs) (regs->ecr.state |= STATE_SCALL_RESTARTED)
+#define syscall_restartable(regs) !(regs->ecr.state &  STATE_SCALL_RESTARTED)
 
 #define current_pt_regs()  \
 ({ \
diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c
index 478768c88f46..f77deb799175 100644
--- a/arch/arc/kernel/asm-offsets.c
+++ b/arch/arc/kernel/asm-offsets.c
@@ -46,7 +46,7 @@ int main(void)
BLANK();
 
DEFINE(PT_status32, offsetof(struct pt_regs, status32));
-   DEFINE(PT_event, offsetof(struct pt_regs, event));
+   DEFINE(PT_event, offsetof(struct pt_regs, ecr));
DEFINE(PT_bta, offsetof(struct pt_regs, bta));
DEFINE(PT_sp, offsetof(struct pt_regs, sp));
DEFINE(PT_r0, offsetof(struct pt_regs, r0));
diff --git a/arch/arc/kernel/kgdb.c b/arch/arc/kernel/kgdb.c
index 345a554c..4f2b5951454f 100644
--- a/arch/arc/kernel/kgdb.c
+++ b/arch/arc/kernel/kgdb.c
@@ -175,7 +175,7 @@ void kgdb_trap(struct pt_regs *regs)
 * with trap_s 4 (compiled) breakpoints, continuation needs to
 * start after the breakpoint.
 */
-   if (regs->ecr_param == 3)
+   if (regs->ecr.param == 3)
instruction_pointer(regs) -= BREAK_INSTR_SIZE;
 
kgdb_handle_exception(1, SIGTRAP, 0, regs);
diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c
index 14ea7406f5cd..e0c233c178b1 100644
--- a/arch/arc/kernel/ptrace.c
+++ b/arch/arc/kernel/ptrace.c
@@ -46,7 +46,7 @@ static const struct pt_regs_offset regoffset_table[] = {
REG_OFFSET_NAME(r0),
REG_OFFSET_NAME(sp),
REG_OFFSET_NAME(orig_r0),
-   REG

[PATCH v2 08/20] ARC: boot log: eliminate struct cpuinfo_arc #4: boot log per ISA

2023-08-17 Thread Vineet Gupta

 - boot log now clearly per ISA
 - global struct cpuinfo_arc[] elimiated
 - local struct struct arcinfo kept for passing info
   between functions

Tested-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202308162101.ve5jbg80-...@intel.com
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/arcregs.h |  33 +-
 arch/arc/include/asm/setup.h   |   4 +-
 arch/arc/kernel/setup.c| 560 +++--
 arch/arc/mm/cache.c|  10 +-
 arch/arc/mm/tlb.c  |   4 +-
 5 files changed, 268 insertions(+), 343 deletions(-)

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 160ee3fab1bd..4b13f60fe7ca 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -23,7 +23,7 @@
 #define ARC_REG_ICCM_BUILD 0x78/* ICCM size (common) */
 #define ARC_REG_XY_MEM_BCR 0x79
 #define ARC_REG_MAC_BCR0x7a
-#define ARC_REG_MUL_BCR0x7b
+#define ARC_REG_MPY_BCR0x7b
 #define ARC_REG_SWAP_BCR   0x7c
 #define ARC_REG_NORM_BCR   0x7d
 #define ARC_REG_MIXMAX_BCR 0x7e
@@ -177,7 +177,7 @@ struct bcr_isa_arcv2 {
 #endif
 };
 
-struct bcr_uarch_build_arcv2 {
+struct bcr_uarch_build {
 #ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:8, prod:8, maj:8, min:8;
 #else
@@ -355,35 +355,6 @@ struct bcr_generic {
 #endif
 };
 
-/*
- ***
- * Generic structures to hold build configuration used at runtime
- */
-
-struct cpuinfo_arc_bpu {
-   unsigned int ver, full, num_cache, num_pred, ret_stk;
-};
-
-struct cpuinfo_arc_ccm {
-   unsigned int base_addr, sz;
-};
-
-struct cpuinfo_arc {
-   struct cpuinfo_arc_bpu bpu;
-   struct bcr_identity core;
-   struct bcr_isa_arcv2 isa;
-   const char *release, *name;
-   unsigned int vec_base;
-   struct cpuinfo_arc_ccm iccm, dccm;
-   struct {
-   unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, 
swape:1, pad1:2,
-fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
-ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
-timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
-   } extn;
-   struct bcr_mpy extn_mpy;
-};
-
 static inline int is_isa_arcv2(void)
 {
return IS_ENABLED(CONFIG_ISA_ARCV2);
diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h
index 4c0bacd0ff5c..1c6db599e1fc 100644
--- a/arch/arc/include/asm/setup.h
+++ b/arch/arc/include/asm/setup.h
@@ -35,10 +35,10 @@ long __init arc_get_mem_sz(void);
 #define IS_AVAIL3(v, v2, s)IS_AVAIL1(v, s), IS_AVAIL1(v, 
IS_DISABLED_RUN(v2))
 
 extern void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
+extern int arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
 
 extern void arc_cache_init(void);
-extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
+extern int arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 
 extern void __init handle_uboot_args(void);
 
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 3ea834941c1f..0aa49308d792 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
 
@@ -43,19 +44,22 @@ const struct machine_desc *machine_desc;
 
 struct task_struct *_current_task[NR_CPUS];/* For stack switching */
 
-struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
+struct cpuinfo_arc {
+   int arcver;
+   unsigned int t0:1, t1:1;
+   struct {
+   unsigned long base;
+   unsigned int sz;
+   } iccm, dccm;
+};
+
+#ifdef CONFIG_ISA_ARCV2
 
-static const struct id_to_str arc_legacy_rel[] = {
+static const struct id_to_str arc_hs_rel[] = {
/* ID.ARCVER,   Release */
-#ifdef CONFIG_ISA_ARCOMPACT
-   { 0x34, "R4.10"},
-   { 0x35, "R4.11"},
-#else
{ 0x51, "R2.0" },
{ 0x52, "R2.1" },
{ 0x53, "R3.0" },
-#endif
-   { 0x00, NULL   }
 };
 
 static const struct id_to_str arc_hs_ver54_rel[] = {
@@ -66,320 +70,294 @@ static const struct id_to_str arc_hs_ver54_rel[] = {
{  3,   "R4.00a"},
{  0xFF,NULL   }
 };
+#endif
 
-static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
+static int
+arcompact_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len)
 {
-   if (is_isa_arcompact()) {
-   struct bcr_iccm_arcompact iccm;
-   struct bcr_dccm_arcompact dccm;
+   int n = 0;
+#ifdef CONFIG_ISA_ARCOMPACT
+   char *cpu_nm, *isa_nm = "ARCompact";
+   struct bcr_fp_arcompact fpu_sp, fpu_dp;
+   int atomic = 0, be, present;
+   int bpu_full, bpu_cac

[PATCH v2 05/20] ARC: boot log: eliminate struct cpuinfo_arc #1: mm

2023-08-17 Thread Vineet Gupta

This is first step in eliminating struct cpuinfo_arc[NR_CPUS]

Back when we had just ARCompact ISA, the idea was to read/bit-fiddle
the BCRs once and and cache decoded information in a global struct ready
to use.

With ARCv2 it was modified to contained abstract / ISA agnostic
information.

However with ARCv3 there 's too much disparity to abstract in common
structures. So drop the entire decode once and store paradigm. Afterall
there's only 2 users of this machinery anyways:  boot printing and
cat /proc/cpuinfo. None is performance critical to warrant locking away
resident memory per cpu.

This patch is first step in that direction
 - decouples struct cpuinfo_arc_mmu from global struct cpuinfo_arc
 - mmu code still has a trimmed down static version of
   struct cpuinfo_arc_mmu to cache information needed in performance
   critical code such as tlb flush routines
 - folds read_decode_mmu_bcr() into arc_mmu_mumbojumbo()
 - setup_processor() directly calls arc_mmu_init() and not via
   arc_cpu_init()

Tested-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202308151213.qkzpmiyz-...@intel.com/
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/arcregs.h | 27 +++---
 arch/arc/include/asm/setup.h   |  1 -
 arch/arc/kernel/setup.c|  4 +-
 arch/arc/mm/tlb.c  | 93 +-
 4 files changed, 58 insertions(+), 67 deletions(-)

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 2162023195c5..af00cbe9b850 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -185,6 +185,27 @@ struct bcr_uarch_build_arcv2 {
 #endif
 };
 
+struct bcr_mmu_3 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+   unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
+u_itlb:4, u_dtlb:4;
+#else
+   unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
+ways:4, ver:8;
+#endif
+};
+
+struct bcr_mmu_4 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+   unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+   /*   DTLB  ITLB  JESJE JA  */
+   unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif
+};
+
 struct bcr_mpy {
 #ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
@@ -307,11 +328,6 @@ struct bcr_generic {
  * Generic structures to hold build configuration used at runtime
  */
 
-struct cpuinfo_arc_mmu {
-   unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
-   unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
-};
-
 struct cpuinfo_arc_cache {
unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
 };
@@ -326,7 +342,6 @@ struct cpuinfo_arc_ccm {
 
 struct cpuinfo_arc {
struct cpuinfo_arc_cache icache, dcache, slc;
-   struct cpuinfo_arc_mmu mmu;
struct cpuinfo_arc_bpu bpu;
struct bcr_identity core;
struct bcr_isa_arcv2 isa;
diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h
index 374138832c5a..76443f198778 100644
--- a/arch/arc/include/asm/setup.h
+++ b/arch/arc/include/asm/setup.h
@@ -36,7 +36,6 @@ long __init arc_get_mem_sz(void);
 
 extern void arc_mmu_init(void);
 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-extern void read_decode_mmu_bcr(void);
 
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 41f07b3e594e..094461540f8a 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -186,7 +186,6 @@ static void read_arc_build_cfg_regs(void)
/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
read_decode_ccm_bcr(cpu);
 
-   read_decode_mmu_bcr();
read_decode_cache_bcr();
 
if (is_isa_arcompact()) {
@@ -256,7 +255,7 @@ static void read_arc_build_cfg_regs(void)
cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 
 /* there's no direct way to distinguish 750 vs. 770 */
-   if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
+   if (unlikely(cpu->core.family < 0x34))
cpu->name = "ARC750";
} else {
cpu->isa = isa;
@@ -463,6 +462,7 @@ void setup_processor(void)
arc_init_IRQ();
 
pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str)));
 
arc_mmu_init();
arc_cache_init();
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 2a3105a682c3..861cabe81e87 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -18,7 +18,9 @@
 /* A copy of the ASID

Re: {standard input}:1727: Error: operand out of range (-132 is not between -128 and 127)

2023-08-15 Thread Vineet Gupta


+CC Alexey and Claudiu

On 8/15/23 09:35, Paul E. McKenney wrote:

On Tue, Aug 15, 2023 at 07:34:04AM +, Liu, Yujie wrote:

Hi Paul,

On Fri, 2023-08-11 at 08:41 -0700, Paul E. McKenney wrote:

On Fri, Aug 11, 2023 at 01:02:12PM +0800, kernel test robot wrote:

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   25aa0bebba72b318e71fe205bfd1236550cc9534
commit: a6889becb05394255c80b62103677e3b095726a9 refscale: Add tests using 
SLAB_TYPESAFE_BY_RCU
date:   7 months ago
config: arc-randconfig-r006-20230811 
(https://download.01.org/0day-ci/archive/20230811/202308111233.rbf5c0jd-...@intel.com/config)
compiler: arceb-elf-gcc (GCC) 12.3.0
reproduce: 
(https://download.01.org/0day-ci/archive/20230811/202308111233.rbf5c0jd-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags

Reported-by: kernel test robot 
Closes: 
https://lore.kernel.org/oe-kbuild-all/202308111233.rbf5c0jd-...@intel.com/

All errors (new ones prefixed by >>):

    {standard input}: Assembler messages:

{standard input}:1727: Error: operand out of range (-132 is not between -128 
and 127)

I am not seeing any inline assembly in that patch, so I have to suspect
a bug in arch code or the compiler backend for arc.

Or is there something that I am missing here?

We looked into this case a little bit. The assembler error popped up
when building kernel/rcu/refscale.o

$make W=1 --keep-going CROSS_COMPILE=arceb-elf- ARCH=arc kernel/rcu/refscale.o
...
   CC [M]  kernel/rcu/refscale.o
{standard input}: Assembler messages:
{standard input}:1727: Error: operand out of range (-132 is not between -128 
and 127)
make[3]: *** [scripts/Makefile.build:252: kernel/rcu/refscale.o] Error 1
make[2]: *** [scripts/Makefile.build:504: kernel/rcu] Error 2
make[2]: Target 'kernel/rcu/refscale.o' not remade because of errors.
make[1]: *** [scripts/Makefile.build:504: kernel] Error 2
make[1]: Target 'kernel/rcu/refscale.o' not remade because of errors.
make: *** [Makefile:2008: .] Error 2
make: Target 'kernel/rcu/refscale.o' not remade because of errors.

We did some assembly and disassembly tricks:

1721 .L334:
1722 ld_sr0,[r14,52] ;15
1723 brgt r0, r19, @.L335
1724 ld_sr0,[r13,120];15
1725 breq_s r0, 0, @.L337
1726 jl [r17]
1727 brne_s r0, 0, @.L337<---
1728 mov_s   r2,20   ;3
1729 mov_s   r1,0;3
1730 mov_s   r0,sp   ;4
1731 jl [r20]
1732 mov_s   r1,0;3
1733 mov_s   r0,sp   ;4
1734 jl @init_wait_entry
1735 .align 2

This assembly instruction at line 1727 points to the code in main_func,
but main_func is not touched by commit a6889becb053.

  d6e:   860dld_sr0,[r14,0x34]
  d70:   0b59 a002   brlt.nt r19,r0,-168 ;cc8 
 return arch_atomic_read(v);
  d74:   851eld_sr0,[r13,0x78]
 wait_event(main_wq,
  d76:   e842breq_s  r0,0,-124   ;cf8 
  d78:   2022 0440   jl  [r17]
  d7c:   e8bebrne_s  r0,0,124;df8
<--
  d7e:   da14mov_s   r2,0x14
  d80:   702cmov_s   r1,0
  d82:   4083mov_s   r0,sp
  d84:   2022 0500   jl  [r20]
  d88:   702cmov_s   r1,0
  d8a:   4083mov_s   r0,sp
  d8c:   2022 0f80   jl  0

We also tried on the parent commit 3c6496c86e48. It builds fine without
that assembler error, and corresponding disassembly is:

  afe:   860dld_sr0,[r14,0x34]
  b00:   0b5d a002   brlt.nt r19,r0,-164 ;a5c 
 return arch_atomic_read(v);
  b04:   8518ld_sr0,[r13,0x60]
 wait_event(main_wq,
  b06:   e844breq_s  r0,0,-120   ;a8c 
  b08:   2022 0440   jl  [r17]
  b0c:   e8c0brne_s  r0,0,-128   ;a8c
<--
  b0e:   da14mov_s   r2,0x14
  b10:   702cmov_s   r1,0
  b12:   4083mov_s   r0,sp
  b14:   2022 0500   jl  [r20]
  b18:   702cmov_s   r1,0
  b1a:   4083mov_s   r0,sp
  b1c:   2022 0f80   jl  0
  b24:   724cmov_s   r2,2
  b26:   4183mov_s   r1,sp
  b28:   40c3    mov_s   r0,0
  b2e:   2022 0f80   jl  0


We are also not sure if this is a bug in arch code or compiler side.
Here we provide above info for your reference.

Thank you for looking into this and getting back to me.

I added the ARC maintainer and list on CC.

Thanx, Paul



___
linux-snps-arc

Re: [PATCH] ARC: avoid unwanted gcc optimizations in atomic operations

2023-08-15 Thread Vineet Gupta





On 8/15/23 08:11, pavel.koz...@synopsys.com wrote:

From: Pavel Kozlov

Notify a compiler about write operations and prevent unwanted
optimizations. Add the "memory" clobber to the clobber list.

An obvious problem with unwanted compiler optimizations appeared after
the cpumask optimization commit 596ff4a09b89 ("cpumask: re-introduce
constant-sized cpumask optimizations").

After this commit the SMP kernels for ARC no longer loads because of
failed assert in the percpu allocator initialization routine:

percpu: BUG: failure at mm/percpu.c:2981/pcpu_build_alloc_info()!

The write operation performed by the scond instruction in the atomic
inline asm code is not properly passed to the compiler. The compiler
cannot correctly optimize a nested loop that runs through the cpumask
in the pcpu_build_alloc_info() function.

Add the "memory" clobber to fix this.

Link:https://github.com/foss-for-synopsys-dwc-arc-processors/linux/issues/135
Cc:  # v6.3+
Signed-off-by: Pavel Kozlov



Acked-by: Vineet Gupta 

Fixes: b64be6836993c431e ("ARC: atomics: implement relaxed variants")

Before that commit, atomic ops could elide memory clobber because the 
trailing smp_mb() did that anyways.
However after that commit, the smp_mb() was optional for relaxed 
variants and thus needs clobber.



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