Re: [PATCH RESEND v9 1/5] arc: dts: Harmonize EHCI/OHCI DT nodes name

2022-06-24 Thread Vineet Gupta



On 6/24/22 07:16, Serge Semin wrote:

In accordance with the Generic EHCI/OHCI bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?"  . Make sure the "generic-ehci" and "generic-ohci"-compatible
nodes are correctly named.

Signed-off-by: Serge Semin
Acked-by: Alexey Brodkin
Acked-by: Krzysztof Kozlowski


This slipped thru cracks. Now on for-curr.

Thx,
-Vineet

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Re: [PATCH] ARC:mm:Fix syntax errors in comments

2022-06-23 Thread Vineet Gupta

On 6/23/22 00:56, Bagas Sanjaya wrote:

In an ideal world yes. But sometimes maintainer complain to break whitespacxe 
fixes and such into independent fix. Also as someone said later in the thread, 
for somebody just getting into kernel and figuring out patch submission etc 
this could be a perfect dry run and helps improve the code anyways.


Seems like you missed the point that it's OK to have typofixes while
doing other real changes (like refactoring) in the same patch.


No I did not.


Quoting from [1]:


My opinion is that trivial patches like this are fine as a starting
point for new contributors, which is why I acked the previous patch from
you guys. However, if we start getting two of these every week it just
adds more maintenance burden than it's worth.

I tend to agree with the last sentence of above quote. Let's pretend that
I'm the tree maintainer. Besides reviewing real change patches, I get
flooded by these similar minor cleanup patches that I need to review.
Some (but not all) these patches have issues (say subject or description
error) that are repeated.


"Repeated" is the key - First time I'd politely tell them to DTRT but 
will just ignore if things continue.



Lazily speaking, I'd like to privately notice the
submitter about the situation, and I withhold these for now.


Funny that you say this: ever since this got posted I now see 3 patches 
for typo fixes :-)

But it is something in maintainers purview and for now i'm ok.

Thx,
-Vineet

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Re: [PATCH] ARC:kernel:Fix typos in comments

2022-06-22 Thread Vineet Gupta




On 6/22/22 00:52, Jilin Yuan wrote:

Delete the redundant word 'call'.

Signed-off-by: Jilin Yuan 
---
  arch/arc/kernel/smp.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index d947473f1e6d..6c22a53711e9 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -393,7 +393,7 @@ irqreturn_t do_IPI(int irq, void *dev_id)
   * API called by platform code to hookup arch-common ISR to their IPI IRQ
   *
   * Note: If IPI is provided by platform (vs. say ARC MCIP), their intc 
setup/map
- * function needs to call call irq_set_percpu_devid() for IPI IRQ, otherwise
+ * function needs to call irq_set_percpu_devid() for IPI IRQ, otherwise
   * request_percpu_irq() below will fail
   */
  static DEFINE_PER_CPU(int, ipi_dev);


I'd prefer to have this is the other fix in a single change. No point 
increasing commits for trivial things.


-Vineet

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Re: [PATCH] ARC:mm:Fix syntax errors in comments

2022-06-22 Thread Vineet Gupta




On 6/22/22 01:30, Bagas Sanjaya wrote:

- * If the U-mapping is not congruent to to K-mapping, former needs flushing.
+ * If the U-mapping is not congruent to K-mapping, former needs flushing.
   */
  void flush_dcache_page(struct page *page)
  {

The patch is OK, but its subject is wrong.


Right.


The patch above isn't fixing any syntax errors, but rather minor cleanup.
The subject should have been "Remove duplicate 'to' in the
flush_dcache_page() comment".


I'd just say "ARC: mm: fix typos"


I think that this kind of cleanup patches (typofixes) are best done
as part of **actual** work on the code in question (for example
refactoring or fixing build errors).


In an ideal world yes. But sometimes maintainer complain to break 
whitespacxe fixes and such into independent fix. Also as someone said 
later in the thread, for somebody just getting into kernel and figuring 
out patch submission etc this could be a perfect dry run and helps 
improve the code anyways.


-Vineet

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Re: [PATCH] ARC: Fix comment typo

2022-06-10 Thread Vineet Gupta




On 5/7/22 20:02, Jason Wang wrote:

Remove one of the repeated 'call' in comment line 396.

Signed-off-by: Jason Wang


Thx for the fix. Added to for-curr

-Vineet

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Re: [PATCH] ARC: Fix syntax errors in comments

2022-06-10 Thread Vineet Gupta




On 6/3/22 06:01, Xiang wangx wrote:

Delete the redundant word 'to'.
Delete the redundant word 'since'.

Signed-off-by: Xiang wangx



Thx for the fix. Added to for-curr

-Vineet

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Re: [PATCH 1/2] ARC: bitops: Change __fls to return unsigned long

2022-05-25 Thread Vineet Gupta

Hi,

On 5/25/22 07:48, Amadeusz Sławiński wrote:

As per asm-generic definition and other architectures __fls should
return unsigned long.

No functional change is expected as return value should fit in unsigned
long.

Signed-off-by: Amadeusz Sławiński


Applied to for-curr.

Thx,
-Vineet

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Re: [PATCH v3] mm: Avoid unnecessary page fault retires on shared memory types

2022-05-25 Thread Vineet Gupta




On 5/24/22 16:45, Peter Xu wrote:

I observed that for each of the shared file-backed page faults, we're very
likely to retry one more time for the 1st write fault upon no page.  It's
because we'll need to release the mmap lock for dirty rate limit purpose
with balance_dirty_pages_ratelimited() (in fault_dirty_shared_page()).

Then after that throttling we return VM_FAULT_RETRY.

We did that probably because VM_FAULT_RETRY is the only way we can return
to the fault handler at that time telling it we've released the mmap lock.

However that's not ideal because it's very likely the fault does not need
to be retried at all since the pgtable was well installed before the
throttling, so the next continuous fault (including taking mmap read lock,
walk the pgtable, etc.) could be in most cases unnecessary.

It's not only slowing down page faults for shared file-backed, but also add
more mmap lock contention which is in most cases not needed at all.

To observe this, one could try to write to some shmem page and look at
"pgfault" value in /proc/vmstat, then we should expect 2 counts for each
shmem write simply because we retried, and vm event "pgfault" will capture
that.

To make it more efficient, add a new VM_FAULT_COMPLETED return code just to
show that we've completed the whole fault and released the lock.  It's also
a hint that we should very possibly not need another fault immediately on
this page because we've just completed it.

This patch provides a ~12% perf boost on my aarch64 test VM with a simple
program sequentially dirtying 400MB shmem file being mmap()ed and these are
the time it needs:

   Before: 650.980 ms (+-1.94%)
   After:  569.396 ms (+-1.38%)

I believe it could help more than that.

We need some special care on GUP and the s390 pgfault handler (for gmap
code before returning from pgfault), the rest changes in the page fault
handlers should be relatively straightforward.

Another thing to mention is that mm_account_fault() does take this new
fault as a generic fault to be accounted, unlike VM_FAULT_RETRY.

I explicitly didn't touch hmm_vma_fault() and break_ksm() because they do
not handle VM_FAULT_RETRY even with existing code, so I'm literally keeping
them as-is.

Signed-off-by: Peter Xu
---

v3:
- Rebase to akpm/mm-unstable
- Copy arch maintainers
---
   arch/arc/mm/fault.c   |  4 ++++


Acked-by: Vineet Gupta 

Thx,
-Vineet

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[GIT PULL] ARC changes for 5.19-rc1

2022-05-25 Thread Vineet Gupta

Hi Linus,

Please pull.

Thx,
-Vineet
--->
The following changes since commit af2d861d4cd2a4da5137f795ee3509e6f944a25b:

  Linux 5.18-rc4 (2022-04-24 14:51:22 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.19-rc1


for you to fetch changes up to 6aa98f6217861889523e38b0141c8c71b2ef8a83:

  ARC: bpf: define uapi for BPF_PROG_TYPE_PERF_EVENT program type 
(2022-04-26 09:35:28 -0700)



ARC changes for 5.19-rc1

 - Basic eBPF support  (Sergey)


Sergey Matyukevich (4):
  ARC: enable HAVE_REGS_AND_STACK_ACCESS_API feature
  ARC: implement syscall tracepoints
  ARC: disasm: handle ARCv2 case in kprobe get/set functions
  ARC: bpf: define uapi for BPF_PROG_TYPE_PERF_EVENT program type

 arch/arc/Kconfig   |   2 +
 arch/arc/include/asm/perf_event.h  |   4 +
 arch/arc/include/asm/ptrace.h  |  27 ++
 arch/arc/include/asm/syscall.h |   2 +
 arch/arc/include/asm/thread_info.h |   5 +-
 arch/arc/include/uapi/asm/bpf_perf_event.h |   9 ++
 arch/arc/kernel/disasm.c   |  64 -
 arch/arc/kernel/entry.S    |  12 +--
 arch/arc/kernel/ptrace.c   | 140 
-

 9 files changed, 253 insertions(+), 12 deletions(-)
 create mode 100644 arch/arc/include/uapi/asm/bpf_perf_event.h

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Re: [vgupta-arc:for-next 3/4] arch/arc/kernel/disasm.c:494:23: error: 'struct pt_regs' has no member named 'gp'; did you mean 'fp'?

2022-04-26 Thread Vineet Gupta

On 4/26/22 00:31, Sergey Matyukevich wrote:

I have just sent a fixup for this snafu:
https://lore.kernel.org/linux-snps-arc/20220426072447.125975-1-geoma...@gmail.com/T/#u

IIUC, you have not yet sent a pull-request for next release. So probably
it makes sense to squash this commit with b08a66fb680018b6 ("ARC: disasm:
handle ARCv2 case in kprobe get/set functions").


Yes this is merge-window stuff so will go in next cycle.
I've added a fixup and push for-next.

Thx,
-Vineet

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[GIT PULL] ARC fixes for 5.18-rc4

2022-04-23 Thread Vineet Gupta

Hi Linus,

Please pull.

Thx,
-Vineet
->
The following changes since commit ce522ba9ef7e2d9fb22a39eb3371c0c64e2a433e:

  Linux 5.18-rc2 (2022-04-10 14:21:36 -1000)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.18-rc4


for you to fetch changes up to c6ed4d84a2c49de7d6f490144cca7b4a4831fb6e:

  ARC: remove redundant READ_ONCE() in cmpxchg loop (2022-04-18 
14:47:05 -0700)



ARC fixes for 5.18-rc4

 - Assorted fixes


Bang Li (1):
  ARC: remove redundant READ_ONCE() in cmpxchg loop

Christophe JAILLET (1):
  ARC: Remove a redundant memset()

Julia Lawall (1):
  ARC: fix typos in comments

Krzysztof Kozlowski (1):
  ARC: dts: align SPI NOR node name with dtschema

Rolf Eike Beer (1):
  arc: drop definitions of pgd_index() and pgd_offset{, _k}() entirely

Sergey Matyukevich (2):
  ARC: entry: fix syscall_trace_exit argument
  ARC: atomic: cleanup atomic-llsc definitions

 arch/arc/boot/dts/hsdk.dts    |  2 +-
 arch/arc/include/asm/atomic-llsc.h    | 32 


 arch/arc/include/asm/pgtable-levels.h |  3 ---
 arch/arc/kernel/disasm.c  |  3 +--
 arch/arc/kernel/entry.S   |  1 +
 arch/arc/kernel/signal.c  |  2 +-
 arch/arc/kernel/smp.c |  4 ++--
 arch/arc/kernel/unaligned.c   |  2 +-
 arch/arc/mm/cache.c   |  2 +-
 9 files changed, 24 insertions(+), 27 deletions(-)

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Re: [PATCH 1/2] ARC: atomic: cleanup atomic-llsc definitions

2022-04-18 Thread Vineet Gupta




On 2/22/22 06:05, Sergey Matyukevich wrote:

From: Sergey Matyukevich

Remove redundant c_op macro argument. Only asm_op is needed
to define atomic operations using llock/scond.

Signed-off-by: Sergey Matyukevich


Applied.

Thx,
-Vineet

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Re: [PATCH] arc: drop definitions of pgd_index() and pgd_offset{, _k}() entirely

2022-04-18 Thread Vineet Gupta




On 3/28/22 01:15, Rolf Eike Beer wrote:

They were in  and have been removed from there in
974b9b2c68f ("mm: consolidate pte_index() and pte_offset_*() definitions")
in favor of the generic version. But that missed that the same definitons
also existed in , where they were (inadvertently?)
introduced in fe6cb7b043b6 ("ARC: mm: disintegrate pgtable.h into levels
and flags").

Fixes: 974b9b2c68f ("mm: consolidate pte_index() and pte_offset_*() 
definitions")
Fixes: fe6cb7b043b6 ("ARC: mm: disintegrate pgtable.h into levels and flags")
Signed-off-by: Rolf Eike Beer


Indeed I missed the upstream change when doing the rework for paging levels.

Applied !

Thx,
-Vineet

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Re: [PATCH] ARC: dts: align SPI NOR node name with dtschema

2022-04-18 Thread Vineet Gupta




On 4/7/22 07:33, Krzysztof Kozlowski wrote:

The node names should be generic and SPI NOR dtschema expects "flash".

Signed-off-by: Krzysztof Kozlowski


Applied.

Thx,
-Vineet

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Re: [PATCH] ARC: Remove a redundant memset()

2022-04-18 Thread Vineet Gupta




On 3/22/22 12:49, Christophe JAILLET wrote:

disasm_instr() already call memset(0) on its 2nd argument, so there is no
need to clear it explicitly before calling this function.

Remove the redundant memset().

Signed-off-by: Christophe JAILLET



Applied.

Thx,
-Vineet

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Re: [PATCH] ARC: fix typos in comments

2022-04-18 Thread Vineet Gupta



On 3/18/22 03:37, Julia Lawall wrote:

Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall


Applied.

Thx,
-Vineet

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Re: [PATCH] ARC: remove redundant READ_ONCE() in cmpxchg loop

2022-04-18 Thread Vineet Gupta




On 3/18/22 19:03, Bang Li wrote:

This patch reverts commit 7082a29c22ac ("ARC: use ACCESS_ONCE in cmpxchg
loop").

It is not necessary to use READ_ONCE() because cmpxchg contains barrier. We
can get it from commit d57f727264f1 ("ARC: add compiler barrier to LLSC
based cmpxchg").

Signed-off-by: Bang Li 


Indeed this is not needed. However have you checked the code with and/wo 
this change to see if it builds the same.


-Vineet


---
  arch/arc/kernel/smp.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 78e6d069b1c1..56c23f3e1309 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -274,7 +274,7 @@ static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg)
 * and read back old value
 */
do {
-   new = old = READ_ONCE(*ipi_data_ptr);
+   new = old = *ipi_data_ptr;
new |= 1U << msg;
} while (cmpxchg(ipi_data_ptr, old, new) != old);
  



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Re: [PATCH v2 2/4] ARC: entry: fix syscall_trace_exit argument

2022-04-18 Thread Vineet Gupta



On 4/14/22 01:17, Sergey Matyukevich wrote:

From: Sergey Matyukevich

Function syscall_trace_exit expects pointer to pt_regs. However
r0 is also used to keep syscall return value. Restore pointer
to pt_regs before calling syscall_trace_exit.

Signed-off-by: Sergey Matyukevich


This is independent fix and worth stable backport, So I'll apply it to 
for-curr, rest of the pile goes for next release.


-Vineet

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Re: [PATCH v2 0/4] ARC: add missing bits for better BPF support

2022-04-18 Thread Vineet Gupta




On 4/14/22 01:17, Sergey Matyukevich wrote:

Hi Vineet and all,

Here is the second revision of the patch series implementing
the following two features for ARC:
- HAVE_REGS_AND_STACK_ACCESS_API
- HAVE_SYSCALL_TRACEPOINTS

Adding these features enables more BPF programs for ARC kernels,
including KPROBE, TRACEPOINT, PERF_EVENT program types.

Regards,
Sergey


Applied !

Thx,
-Vineet



v1 -> v2:

- drop path with uapi for BPF_PROG_TYPE_PERF_EVENT program type: send it via 
bpf mailing list
- add patch with ARCv2 changes for kprobe disasm

Sergey Matyukevich (4):
   ARC: enable HAVE_REGS_AND_STACK_ACCESS_API feature
   ARC: entry: fix syscall_trace_exit argument
   ARC: implement syscall tracepoints
   ARC: disasm: handle ARCv2 case in kprobe get/set functions

  arch/arc/Kconfig   |   2 +
  arch/arc/include/asm/ptrace.h  |  27 ++
  arch/arc/include/asm/syscall.h |   2 +
  arch/arc/include/asm/thread_info.h |   5 +-
  arch/arc/kernel/disasm.c   |  64 -
  arch/arc/kernel/entry.S|  13 +--
  arch/arc/kernel/ptrace.c   | 140 -
  7 files changed, 241 insertions(+), 12 deletions(-)




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Re: [RFC PATCH 00/13] ARC: handle the lack of ZOL support

2022-02-27 Thread Vineet Gupta
Thx for doing this. I think the series mixes a few things not related to 
ZOL removal - the changelog for removal of -Os specific code seems 
incorrect etc.

Let me repost with slight more cleanups.

-Vineet

On 2/22/22 06:14, Sergey Matyukevich wrote:

From: Sergey Matyukevich 

Hi Vineet and all,

This patch series continues to prepare arch/arc for the upcoming ARCv3
support. ARCv3 does not support zero-overhead-loop (ZOL). So this patch
series provides a set of changes that make ZOL support optional.

The patch series is based on top of Linux 5.17-rc5. It has been tested
with enabled CONFIG_ARC_LACKS_ZOL option on ARCv2 HSDK hardware as well
as on nSIM simulator for ARCv2.

I fixed typos, updated Vineet's email address, and slightly modified
several commit messages. Otherwise this patch series is the first chunk
of ARCv3 bring-up changes by Vineet, available at Synopsys github: see
github.com/foss-for-synopsys-dwc-arc-processors/linux

Regards,
Sergey

Vineet Gupta (13):
   ARC: uaccess: elide unaliged handling if hardware supports
   ARC: Kconfig: introduce option to disable ZOL
   ARC: uaccess: drop CC_OPTIMIZE_FOR_SIZE
   ARC: uaccess: elide ZOL, use double load/stores
   ARCv2: memset: don't prefetch for len == 0 which happens a lot
   ARCv2: memset: elide unaligned handling if hardware supports
   ARCv2: memset: rewrite using double load/stores
   ARC: string: use generic C code if no ZOL support
   ARC: delay: elide ZOL
   ARC: checksum: elide ZOL
   ARC: head: elide ZOL
   ARC: build: inhibit ZOL generation by compiler
   ARC: pt_regs: handle the case when ZOL is not supported

  arch/arc/Kconfig   |  10 ++
  arch/arc/Makefile  |   3 +
  arch/arc/include/asm/asm-macro-dbnz-emul.h |  12 ++
  arch/arc/include/asm/asm-macro-dbnz.h  |   8 ++
  arch/arc/include/asm/asm-macro-ll64-emul.h |  31 +
  arch/arc/include/asm/asm-macro-ll64.h  |  20 +++
  arch/arc/include/asm/assembler.h   |  41 ++
  arch/arc/include/asm/checksum.h|  58 +++-
  arch/arc/include/asm/delay.h   |  16 +++
  arch/arc/include/asm/entry-arcv2.h |   4 +
  arch/arc/include/asm/entry.h   |   2 +
  arch/arc/include/asm/ptrace.h  |   4 +-
  arch/arc/include/asm/string.h  |  15 ++-
  arch/arc/include/asm/uaccess.h |  29 ++--
  arch/arc/kernel/arcksyms.c |   2 +
  arch/arc/kernel/asm-offsets.c  |   2 +
  arch/arc/kernel/disasm.c   |   2 +
  arch/arc/kernel/head.S |   8 +-
  arch/arc/kernel/intc-arcv2.c   |   2 +
  arch/arc/kernel/kgdb.c |   4 +
  arch/arc/kernel/process.c  |   2 +
  arch/arc/kernel/ptrace.c   |  12 ++
  arch/arc/kernel/signal.c   |   8 ++
  arch/arc/kernel/troubleshoot.c |   3 +
  arch/arc/kernel/unaligned.c|   2 +
  arch/arc/kernel/vmlinux.lds.S  |   2 +-
  arch/arc/lib/Makefile  |   6 +
  arch/arc/lib/memset-archs.S| 147 +
  arch/arc/lib/uaccess.S | 144 
  arch/arc/mm/extable.c  |  11 --
  30 files changed, 493 insertions(+), 117 deletions(-)
  create mode 100644 arch/arc/include/asm/asm-macro-dbnz-emul.h
  create mode 100644 arch/arc/include/asm/asm-macro-dbnz.h
  create mode 100644 arch/arc/include/asm/asm-macro-ll64-emul.h
  create mode 100644 arch/arc/include/asm/asm-macro-ll64.h
  create mode 100644 arch/arc/include/asm/assembler.h
  create mode 100644 arch/arc/lib/uaccess.S




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Re: [RFC PATCH 0/3] arc: remove CONFIG_SET_FS

2022-02-17 Thread Vineet Gupta




IIUC it makes sense to drop this patch series from your for-next branch.
These changes have been superseded by generic approach posted by
Arnd Bergmann, see:
https://lore.kernel.org/linux-arch/CAHk-=whXYWoP6of7js=f4zov62on97mnfrsvrwhy75wogm6...@mail.gmail.com/T/#t

I tested patches by Arnd on ARC700/ARCHS platforms, so far so good.


Yep I've been following that thread and have dropped your ARC patchset. 
Thx for testing. You can reply to Arnd with a

Tested-by: < your-name> #arc

-Vineet

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Re: [RFC PATCH 0/3] arc: remove CONFIG_SET_FS

2022-02-01 Thread Vineet Gupta

On 2/1/22 06:55, Sergey Matyukevich wrote:

Hi all,

This patch series removes SET_FS support for arc.

Sergey Matyukevich (3):
   arc: use BUILD_BUG for invalid sizes in get_user/put_user
   arc: provide __{get,put}_kernel_nofault
   arc: remove set_fs()

  arch/arc/Kconfig   |  1 -
  arch/arc/include/asm/segment.h | 20 -
  arch/arc/include/asm/thread_info.h |  3 --
  arch/arc/include/asm/uaccess.h | 48 --
  4 files changed, 32 insertions(+), 40 deletions(-)
  delete mode 100644 arch/arc/include/asm/segment.h


Nit - in future please use uppercase "ARC" for prefixing patches.

Added to for-next.

Thx,
-Vineet

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[GIT PULL] ARC updates for 5.17-rc1

2022-01-16 Thread Vineet Gupta

Hi Linus,

ARC fixes for 5.17. Nothing too exciting for now.

Thx,
-Vineet
--->
The following changes since commit fc74e0a40e4f9fd0468e34045b0c45bba11dcbb2:

  Linux 5.16-rc7 (2021-12-26 13:17:17 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.17-rc1


for you to fetch changes up to 8f67f65d121cc3bbb4ffaae80e880aeb307d49f4:

  arc: use swap() to make code cleaner (2021-12-28 19:49:44 -0800)


Fixes for ARC for 5.17


Alexey Brodkin (1):
  arc: perf: Move static structs to where they're really used

Colin Ian King (1):
  ARC: perf: Remove redundant initialization of variable idx

Kees Cook (1):
  arc: Replace lkml.org links with lore

Randy Dunlap (1):
  ARC: thread_info.h: correct two typos in a comment

Vineet Gupta (1):
  ARC: perf: fix misleading comment about pmu vs counter stop

Yihao Han (1):
  arc: use swap() to make code cleaner

 arch/arc/include/asm/irqflags-compact.h |   8 +-
 arch/arc/include/asm/perf_event.h   | 162 
---

 arch/arc/include/asm/thread_info.h  |   4 +-
 arch/arc/kernel/perf_event.c    | 166 
+++-

 arch/arc/kernel/unwind.c    |  11 +--
 arch/arc/mm/dma.c   |   2 +-
 arch/arc/plat-axs10x/axs10x.c   |   2 +-
 arch/arc/plat-hsdk/platform.c   |   2 +-
 8 files changed, 178 insertions(+), 179 deletions(-)

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Re: [PATCH] ARC: dw2 unwind: use swap() to make code cleaner

2021-12-28 Thread Vineet Gupta

On 11/9/21 9:56 PM, cgel@gmail.com wrote:

From: Ye Guojin 

This was found by coccicheck:
./arch/arc/kernel/unwind.c, 251, 22-23, WARNING opportunity for swap()
./arch/arc/kernel/unwind.c, 254, 18-19, WARNING opportunity for swap()

Addtionally, adjust the sequence of header files to be arranged in
alphabetical order.

Reported-by: Zeal Robot 
Signed-off-by: Ye Guojin 
---
  arch/arc/kernel/unwind.c | 26 +++---
  1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/arch/arc/kernel/unwind.c b/arch/arc/kernel/unwind.c
index 9e28058cdba8..ea795304982a 100644
--- a/arch/arc/kernel/unwind.c
+++ b/arch/arc/kernel/unwind.c
@@ -10,17 +10,18 @@
   * is not much point in implementing the full Dwarf2 unwind API.
   */
  
-#include 

-#include 
+#include 
+#include 
+#include 


No this is not correct. We always include linux/* first followed by any 
specific arch asm/* includes.



  #include 
-#include 
+#include 
+#include 
+#include 
+#include 
  #include 
+#include 
  #include 
  #include 
-#include 
-#include 
-#include 
-#include 


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Re: [PATCH] arc: use swap() to make code cleaner

2021-12-28 Thread Vineet Gupta

On 11/9/21 7:07 PM, Yihao Han wrote:

Use the macro 'swap()' defined in 'include/linux/minmax.h' to avoid
opencoding it.

Signed-off-by: Yihao Han


Added to ARC tree.

Thx,
-Vineet

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Re: [PATCH] arc: perf: Move static structs to where they're really used

2021-12-28 Thread Vineet Gupta

On 11/29/21 12:37 PM, Alexey Brodkin wrote:

It is all well described by Stephen Rothwell who initially spotted that:
->8
After merging the origin tree, today's linux-next build (arc
haps_hs_smp_defconfig+kselftest) produced these warnings:

arch/arc/include/asm/perf_event.h:126:27: warning: 'arc_pmu_cache_map' defined 
but not used [-Wunused-const-variable=]
arch/arc/include/asm/perf_event.h:91:27: warning: 'arc_pmu_ev_hw_map' defined 
but not used [-Wunused-const-variable=]

Introduced by commit 0dd450fe13da ("ARC: Add perf support for ARC700 cores")

The 2 static arrays should be moved into arch/arc/kernel/perf_event.c
(the only place that uses them). We get the warning because perf_event.h
is also included by arch/arc/kernel/unaligned.c.
->8

Could be easily reproduced by running make with "W=1" on any up-to-date
sources, when extra warnings get enabled (in particular
"-Wunused-const-variable"), otherwise disabled by default in the top-level
Makefile as "These warnings generated too much noise in a regular build".

Signed-off-by: Alexey Brodkin
Cc: Stephen Rothwell
Cc: Mischa Jonker
Cc: Vineet Gupta


Added to ARC tree.

Thx,
-Vineet

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Re: [PATCH] ARC: perf: Remove redundant initialization of variable idx

2021-12-28 Thread Vineet Gupta

On 11/26/21 2:23 PM, Colin Ian King wrote:

The variable idx is being initialized with a value that is never
read, it is being updated later on. The assignment is redundant and
can be removed.

Signed-off-by: Colin Ian King


Sorry for the delay in getting to this. Added to ARC tree now.

Thx,
-Vineet

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Re: [PATCH 2/2] futex: remove futex_cmpxchg detection

2021-10-30 Thread Vineet Gupta

On 10/26/21 3:03 AM, Arnd Bergmann wrote:

From: Arnd Bergmann 

Now that all architectures have a working futex implementation
in any configuration, remove the runtime detection code.

Signed-off-by: Arnd Bergmann 
---
  arch/arc/Kconfig  |  1 -


Acked-by: Vineet Gupta   #arch/arc

Thx,
-Vineet

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Re: [PATCH] ARC: thread_info.h: correct two typos in a comment

2021-10-30 Thread Vineet Gupta



On 10/29/21 5:31 PM, Randy Dunlap wrote:

Fix typos of "separately" and "remains".

Signed-off-by: Randy Dunlap 
Suggested-by: Matthew Wilcox  # "remains"
Cc: Vineet Gupta 
Cc: linux-snps-arc@lists.infradead.org


Thx for the fix. Added to for-curr.

-Vineet




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[GIT PULL] ARC fix for 5.15-rc6

2021-10-15 Thread Vineet Gupta

Hi Linus,

Fixlet for ARC, better to go in now. Please pull !

Thx,
-Vineet
--->
The following changes since commit 64570fbc14f8d7cb3fe3995f20e26bc25ce4b2cc:

  Linux 5.15-rc5 (2021-10-10 17:01:59 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.15-rc6


for you to fetch changes up to c3ca31ce0ea1e1ae34748ded54b6ccc319e7ed20:

  ARC: fix potential build snafu (2021-10-15 18:06:32 -0700)


Small fixlet for ARC

----
Vineet Gupta (1):
  ARC: fix potential build snafu

 arch/arc/include/asm/pgtable.h | 5 -
 1 file changed, 5 deletions(-)


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Re: [PATCH v2] clocksource: arc_timer: eliminate redefined macro error

2021-09-23 Thread Vineet Gupta




On 9/23/21 7:08 PM, Randy Dunlap wrote:

In drivers/clocksource/, 3 drivers use "TIMER_CTRL_IE" with 3 different
values.  Two of them (mps2-timer.c and timer-sp804.c/timer-sp.h) are
localized and left unmodifed.

One of them uses a shared header file (), which is
what is causing the "redefined" warnings, so change the macro name in
that driver only. Also change the TIMER_CTRL_NH macro name.
Both macro names are prefixed with "ARC_" to reduce the likelihood
of future name collisions.

In file included from ../drivers/clocksource/timer-sp804.c:24:
../drivers/clocksource/timer-sp.h:25: error: "TIMER_CTRL_IE" redefined [-Werror]
25 | #define TIMER_CTRL_IE   (1 << 5)/*   VR */
../include/soc/arc/timers.h:20: note: this is the location of the previous 
definition
20 | #define TIMER_CTRL_IE   (1 << 0) /* Interrupt when Count 
reaches limit */

Fixes: b26c2e3823ba ("ARC: breakout timer include code into separate header")
Signed-off-by: Randy Dunlap 
Cc: Vineet Gupta 
Cc: linux-snps-arc@lists.infradead.org
Cc: Daniel Lezcano 
Cc: Thomas Gleixner 
Cc: Shahab Vahedi 


Acked-by: Vineet Gupta 

Thx,
-Vineet


---
v2: prefix both TIMER_CTRL_xx macros with ARC_ (suggested by
 Shahab Vahedi 

  drivers/clocksource/arc_timer.c |6 +++---
  include/soc/arc/timers.h|4 ++--
  2 files changed, 5 insertions(+), 5 deletions(-)

--- linux-next-20210917.orig/include/soc/arc/timers.h
+++ linux-next-20210917/include/soc/arc/timers.h
@@ -17,8 +17,8 @@
  #define ARC_REG_TIMER1_CNT0x100   /* timer 1 count */
  
  /* CTRL reg bits */

-#define TIMER_CTRL_IE  (1 << 0) /* Interrupt when Count reaches limit 
*/
-#define TIMER_CTRL_NH  (1 << 1) /* Count only when CPU NOT halted */
+#define ARC_TIMER_CTRL_IE  (1 << 0) /* Interrupt when Count reaches limit 
*/
+#define ARC_TIMER_CTRL_NH  (1 << 1) /* Count only when CPU NOT halted */
  
  #define ARC_TIMERN_MAX		0x
  
--- linux-next-20210917.orig/drivers/clocksource/arc_timer.c

+++ linux-next-20210917/drivers/clocksource/arc_timer.c
@@ -225,7 +225,7 @@ static int __init arc_cs_setup_timer1(st
  
  	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);

write_aux_reg(ARC_REG_TIMER1_CNT, 0);
-   write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
+   write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH);
  
  	sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
  
@@ -245,7 +245,7 @@ static void arc_timer_event_setup(unsign

write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
  
-	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);

+   write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | 
ARC_TIMER_CTRL_NH);
  }
  
  
@@ -294,7 +294,7 @@ static irqreturn_t timer_irq_handler(int

 *  explicitly clears IP bit
 * 2. Re-arm interrupt if periodic by writing to IE bit [0]
 */
-   write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
+   write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH);
  
  	evt->event_handler(evt);
  



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[GIT PULL] ARC changes for 5.15-rc1

2021-09-04 Thread Vineet Gupta

Hi Linus,

Finally a big pile of changes for ARC (atomics/mm). These are from our 
internal arc64 tree, preparing mainline for eventual arc64 support. I'm 
spreading them to avoid tsunami of patches in one release. Please pull.


Thx,
-Vineet
--->

The following changes since commit e22ce8eb631bdc47a4a4ea7ecf4e4ba499db4f93:

  Linux 5.14-rc7 (2021-08-22 14:24:56 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.15-rc1


for you to fetch changes up to 56809a28d45fcad94b28cfd614600568c0d46545:

  ARC: mm: vmalloc sync from kernel to user table to update PMD ... 
(2021-08-26 13:43:19 -0700)



ARC changes for v5.15-rc1

 - MM rework
   + Implementing up to 4 paging levels (needed in MMUv6)
   + Enable STRICT_MM_TYPECHECK
   + switch pgtable_t back to struct page *

 - Atomics rework / implementing relaxed accessors

 - Retiring support for legacy ARC750 cores and MMUv1,v2

 - A few other build errors, typos


Changcheng Deng (1):
  arch/arc/kernel/: fix misspellings using codespell tool

Randy Dunlap (1):
  ARC: export clear_user_page() for modules

Vineet Gupta (31):
  ARC: atomics: disintegrate header
  ARC: atomic: !LLSC: remove hack in atomic_set() for for UP
  ARC: atomic: !LLSC: use int data type consistently
  ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return
  ARC: atomics: implement relaxed variants
  ARC: switch to generic bitops
  ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines
  ARC: xchg: !LLSC: remove UP micro-optimization/hack
  ARC: cmpxchg/xchg: rewrite as macros to make type safe
  ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only)
  ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants
  ARC: retire ARC750 support
  ARC: retire MMUv1 and MMUv2 support
  ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only
  ARC: mm: remove tlb paranoid code
  ARC: mm: move mmu/cache externs out to setup.h
  ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS
  ARC: mm: Enable STRICT_MM_TYPECHECKS
  ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag
  ARC: mm: pmd_populate* to use the canonical set_pmd (and drop 
pmd_set)

  ARC: mm: non-functional code movement/cleanup
  ARC: mm: move MMU specific bits out of ASID allocator
  ARC: mm: move MMU specific bits out of entry code ...
  ARC: mm: disintegrate mmu.h (arcv2 bits out)
  ARC: mm: disintegrate pgtable.h into levels and flags
  ARC: mm: hack to allow 2 level build with 4 level code
  ARC: mm: switch pgtable_t back to struct page *
  ARC: mm: switch to asm-generic/pgalloc.h
  ARC: mm: support 3 levels of page tables
  ARC: mm: support 4 levels of page tables
  ARC: mm: vmalloc sync from kernel to user table to update PMD ...

 arch/arc/Kconfig |  41 +--
 arch/arc/include/asm/atomic-llsc.h |  97 +++
 arch/arc/include/asm/atomic-spinlock.h | 102 +++
 arch/arc/include/asm/atomic.h | 444 ++
 arch/arc/include/asm/atomic64-arcv2.h | 250 +
 arch/arc/include/asm/bitops.h | 188 +
 arch/arc/include/asm/cache.h |   4 -
 arch/arc/include/asm/cmpxchg.h | 233 
 arch/arc/include/asm/entry-compact.h |   8 -
 arch/arc/include/asm/hugepage.h |   8 -
 arch/arc/include/asm/mmu-arcv2.h | 103 +++
 arch/arc/include/asm/mmu.h |  87 +-
 arch/arc/include/asm/mmu_context.h |  28 +-
 arch/arc/include/asm/page.h |  74 +++--
 arch/arc/include/asm/pgalloc.h |  81 ++
 arch/arc/include/asm/pgtable-bits-arcv2.h | 149 ++
 arch/arc/include/asm/pgtable-levels.h | 189 +
 arch/arc/include/asm/pgtable.h | 339 +--
 arch/arc/include/asm/processor.h |   2 +-
 arch/arc/include/asm/setup.h |  12 +-
 arch/arc/include/asm/smp.h |  14 -
 arch/arc/include/asm/tlb-mmu1.h | 101 ---
 arch/arc/kernel/entry-arcv2.S |   1 +
 arch/arc/kernel/entry.S |   7 +-
 arch/arc/kernel/intc-compact.c |   2 +-
 arch/arc/kernel/smp.c |   4 +-
 arch/arc/kernel/stacktrace.c |   2 +-
 arch/arc/mm/cache.c | 112 +---
 arch/arc/mm/fault.c |  20 +-
 arch/arc/mm/init.c |   5 +
 arch/arc/mm/ioremap.c |   3 +-
 arch/arc/mm/tlb.c | 268 +++---
 arch/arc/mm/tlbex.S |  84 ++
 33 files changed, 1226 insertions(+), 1836 deletions(-)
 create mode 100644 arch/arc/include/asm/atomic-llsc.h
 create mode 100644 arch/arc/include/asm/atomic-spinlock.h
 create mode 100644 arch/arc/include/asm/atomic64-arcv2.h
 create mode 100644 arch/arc/include/asm/mmu-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-levels.h
 delete mode 100644 arch/arc/include/asm/tlb-mmu

Re: [arc:for-next 29/33] arch/arc/include/asm/page.h:52:30: error: 'struct page' has no member named 'pte'; did you mean 'ptl'?

2021-08-26 Thread Vineet Gupta

On 8/26/21 1:35 AM, kernel test robot wrote:

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git for-next
head:   c80ef1151c91db05e9ed03d7b61ada7af63ce59a
commit: 4058fa6bf4da7f46a57cb33fe8f6b688052b3eb9 [29/33] ARC: mm: switch 
pgtable_t back to struct page *
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
 wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
 chmod +x ~/bin/make.cross
 # 
https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/commit/?id=4058fa6bf4da7f46a57cb33fe8f6b688052b3eb9
 git remote add arc 
https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
 git fetch --no-tags arc for-next
 git checkout 4058fa6bf4da7f46a57cb33fe8f6b688052b3eb9
 # save the attached .config to linux build tree
 mkdir build_dir
 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross 
O=build_dir ARCH=arc SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

arch/arc/mm/tlb.c:392:6: warning: no previous prototype for 'create_tlb' 
[-Wmissing-prototypes]
  392 | void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, 
pte_t *ptep)
  |  ^~
In file included from include/linux/mm_types_task.h:16,
 from include/linux/mm_types.h:5,
 from include/linux/buildid.h:5,
 from include/linux/module.h:14,
 from arch/arc/mm/tlb.c:9:
arch/arc/mm/tlb.c: In function 'pgtable_trans_huge_withdraw':

arch/arc/include/asm/page.h:52:30: error: 'struct page' has no member named 
'pte'; did you mean 'ptl'?

   52 | #define pte_val(x)  ((x).pte)
  |  ^~~
arch/arc/mm/tlb.c:568:9: note: in expansion of macro 'pte_val'
  568 | pte_val(pgtable[0]) = 0;
  | ^~~

arch/arc/include/asm/page.h:52:30: error: 'struct page' has no member named 
'pte'; did you mean 'ptl'?

   52 | #define pte_val(x)  ((x).pte)
  |  ^~~
arch/arc/mm/tlb.c:569:9: note: in expansion of macro 'pte_val'
  569 | pte_val(pgtable[1]) = 0;
  | ^~~
arch/arc/mm/tlb.c: At top level:
arch/arc/mm/tlb.c:756:6: warning: no previous prototype for 
'do_tlb_overlap_fault' [-Wmissing-prototypes]
  756 | void do_tlb_overlap_fault(unsigned long cause, unsigned long 
address,
  |  ^~~~



Thx for the report. I've fixed this up by removing the now not-needed 
__HAVE_ARCH_PGTABLE_DEPOSIT and __HAVE_ARCH_PGTABLE_WITHDRAW from ARC code.


-Vineet


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Re: [PATCH] ARC: export clear_user_page() for modules

2021-08-16 Thread Vineet Gupta

On 8/16/21 2:05 PM, Randy Dunlap wrote:

0day bot reports a build error:
   ERROR: modpost: "clear_user_page" 
[drivers/media/v4l2-core/videobuf-dma-sg.ko] undefined!
so export it in arch/arc/ to fix the build error.

In most ARCHes, clear_user_page() is a macro. OTOH, in a few
ARCHes it is a function and needs to be exported.
PowerPC exported it in 2004. It looks like nds32 and nios2
still need to have it exported.

Fixes: 4102b53392d63 ("ARC: [mm] Aliasing VIPT dcache support 2/4")
Signed-off-by: Randy Dunlap 
Reported-by: kernel test robot 
Cc: Guenter Roeck 
Cc: Vineet Gupta 
Cc: linux-snps-arc@lists.infradead.org


Thx for the fix. Added for 5.16 !

-Vineet


---
  arch/arc/mm/cache.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-next-20210816.orig/arch/arc/mm/cache.c
+++ linux-next-20210816/arch/arc/mm/cache.c
@@ -1041,7 +1041,7 @@ void clear_user_page(void *to, unsigned
clear_page(to);
clear_bit(PG_dc_clean, >flags);
  }
-
+EXPORT_SYMBOL(clear_user_page);
  
  /**

   * Explicit Cache flush request from user space via syscall

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Re: [PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc

2021-08-16 Thread Vineet Gupta

On 8/15/21 2:26 AM, Mike Rapoport wrote:

On Thu, Aug 12, 2021 at 04:37:34PM -0700, Vineet Gupta wrote:

Hi,

Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from
current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based
cores).

Most of these changes are incremental cleanups to make way for 14/18 and
15/18 which actually imeplement the new levels (in existing ARCv2 port)
and worth a critical eye.

CC'ing some of you guys dealing with page tables for a while :-)
to spot any obvious gotchas.

There are a couple of small nits here and there, but overall


I've fixed the last remaining things locally and won't repost, unless 
you want me to.




Acked-by: Mike Rapoport 


Thx for spending time to review this Mike. Much appreciated.


-Vineet




Thx,
-Vineet

Changes since v1 [1]
  - Switched ARC to asm-generic/pgalloc.h  (so struct page based pgtable_t) 
 [Mike Rapoport]
  - Dropped {pud,pmd}_alloc_one/{pud,pmd}_free provided by 
asm-generic/pgalloc.h [Mike Rapoport]
  - Negative diffstat now due to above
  - Added BUILD_BUG_ON() to arch/arc/mm/init.c for sanity of table sizes
  - Consolidated 2 patches related to ARC_USE_SCRATCH_REG   
   [Mike Rapoport]
  - Reworked how mmu is re-enabled in entry code
 [Jose Abreu]

[1] http://lists.infradead.org/pipermail/linux-snps-arc/2021-August/005326.html

Vineet Gupta (19):
   ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only
   ARC: mm: remove tlb paranoid code
   ARC: mm: move mmu/cache externs out to setup.h
   ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS
   ARC: mm: Enable STRICT_MM_TYPECHECKS
   ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag
   ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)
   ARC: mm: switch pgtable_t back to struct page *
   ARC: mm: switch to asm-generic/pgalloc.h
   ARC: mm: non-functional code cleanup ahead of 3 levels
   ARC: mm: move MMU specific bits out of ASID allocator
   ARC: mm: move MMU specific bits out of entry code ...
   ARC: mm: disintegrate mmu.h (arcv2 bits out)
   ARC: mm: disintegrate pgtable.h into levels and flags
   ARC: mm: hack to allow 2 level build with 4 level code
   ARC: mm: support 3 levels of page tables
   ARC: mm: support 4 levels of page tables
   ARC: mm: vmalloc sync from kernel to user table to update PMD ...
   ARC: mm: introduce _PAGE_TABLE to explicitly link pgd,pud,pmd entries

  arch/arc/Kconfig  |   7 +-
  arch/arc/include/asm/cache.h  |   4 -
  arch/arc/include/asm/entry-compact.h  |   8 -
  arch/arc/include/asm/mmu-arcv2.h  | 103 +++
  arch/arc/include/asm/mmu.h|  73 +
  arch/arc/include/asm/mmu_context.h|  28 +-
  arch/arc/include/asm/page.h   |  74 +++--
  arch/arc/include/asm/pgalloc.h|  81 ++
  arch/arc/include/asm/pgtable-bits-arcv2.h | 151 +++
  arch/arc/include/asm/pgtable-levels.h | 179 
  arch/arc/include/asm/pgtable.h| 315 +-
  arch/arc/include/asm/processor.h  |   2 +-
  arch/arc/include/asm/setup.h  |  12 +-
  arch/arc/kernel/entry-arcv2.S |   1 +
  arch/arc/kernel/entry.S   |   7 +-
  arch/arc/mm/fault.c   |  20 +-
  arch/arc/mm/init.c|   5 +
  arch/arc/mm/ioremap.c |   3 +-
  arch/arc/mm/tlb.c |  68 +
  arch/arc/mm/tlbex.S   |  78 ++
  20 files changed, 591 insertions(+), 628 deletions(-)
  create mode 100644 arch/arc/include/asm/mmu-arcv2.h
  create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
  create mode 100644 arch/arc/include/asm/pgtable-levels.h

--
2.25.1




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Re: [PATCH v2 16/19] ARC: mm: support 3 levels of page tables

2021-08-16 Thread Vineet Gupta

On 8/15/21 2:27 AM, Mike Rapoport wrote:

On Thu, Aug 12, 2021 at 04:37:50PM -0700, Vineet Gupta wrote:

ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
Forthcoming hw will have multiple levels, so this change preps mm code
for same. It is also fun to try multi levels even on soft-walked code to
ensure generic mm code is robust to handle.

overview


2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on 
pgd
3 levels {pgd, pmd, pte}:
   - pud is folded and pud_* macros point to pgd
   - pmd_* macros operate on actual pmd

code changes


1. #include 

2. Define CONFIG_PGTABLE_LEVELS 3

3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t
3b. Define pmd_val() which actually deals with pmd
 (pmd_offset(), pmd_index() are provided by generic code)
3c. pmd_alloc_one()/pmd_free() also provided by generic code
 (pmd_populate/pmd_free already exist)

4. Define pud_none(), pud_bad() macros based on generic pud_val() which
internally pertains to pgd now.
4b. define pud_populate() to just setup pgd

Signed-off-by: Vineet Gupta 
---

...


diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 8ece75335bb5..1c2f022d4ad0 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -10,6 +10,8 @@
  #ifndef _ASM_ARC_PGTABLE_LEVELS_H
  #define _ASM_ARC_PGTABLE_LEVELS_H
  
+#if CONFIG_PGTABLE_LEVELS == 2

+
  /*
   * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
   *
@@ -37,16 +39,38 @@
  #define PGDIR_SHIFT   21
  #endif
  
-#define PGDIR_SIZE		BIT(PGDIR_SHIFT)	/* vaddr span, not PDG sz */

-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+#else

Adding /* CONFIG_PGTABLE_LEVELS == 2 */ would make the whole thing a bit
more readable, I think.


You meant

+#else /* CONFIG_PGTABLE_LEVELS != 2




+
+/*
+ * A default 3 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ */
+#define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SHIFT  21
+#endif
+
+#endif

and here as well.


I added following to indicate conditional coding for levels related code

+#endif /* CONFIG_PGTABLE_LEVELS */


   

+#define PGDIR_SIZE BIT(PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
  #define PTRS_PER_PGD  BIT(32 - PGDIR_SHIFT)
  
-#define PTRS_PER_PTE		BIT(PGDIR_SHIFT - PAGE_SHIFT)

+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SIZE   BIT(PMD_SHIFT)
+#define PMD_MASK   (~(PMD_SIZE - 1))
+#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)
+#endif
+
+#define PTRS_PER_PTE   BIT(PMD_SHIFT - PAGE_SHIFT)
  



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Re: [PATCH v2 03/19] ARC: mm: move mmu/cache externs out to setup.h

2021-08-16 Thread Vineet Gupta

On 8/15/21 2:27 AM, Mike Rapoport wrote:

Heh,

"Don't pollute mmu.h and cache.h with some of ARC internal bootlog/setup
related functions.
move them aside to setup.h"

is still not there :)


Oops my bad, indeed missed out on that one. Fixed now.

Thx,
-Vineet


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Re: [PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

2021-08-16 Thread Vineet Gupta

On 8/15/21 2:27 AM, Mike Rapoport wrote:

On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote:

MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
ARC700 SMP port, it has to be repurposed for reentrant interrupt
handling, while UP port doesn't. We  currently ahandle boe usecases

   ^ handle both

maybe ':set spell' for changelog editing? ;-)


Seriously, about time I stopped fat-fingering

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Re: [PATCH v6 00/12] mm/debug_vm_pgtable: Enhancements

2021-08-13 Thread Vineet Gupta

On 8/13/21 2:25 AM, Gavin Shan wrote:

Hi Anshuman and Vineet,

On 8/12/21 9:11 PM, Anshuman Khandual wrote:

On 8/9/21 2:56 PM, Gavin Shan wrote:

There are couple of issues with current implementations and this series
tries to resolve the issues:

   (a) All needed information are scattered in variables, passed to 
various
   test functions. The code is organized in pretty much relaxed 
fashion.


   (b) The page isn't allocated from buddy during page table entry 
modifying
   tests. The page can be invalid, conflicting to the 
implementations
   of set_xxx_at() on ARM64. The target page is accessed so that 
the
   iCache can be flushed when execution permission is given on 
ARM64.
   Besides, the target page can be unmapped and accessing to it 
causes

   kernel crash.

"struct pgtable_debug_args" is introduced to address issue (a). For 
issue
(b), the used page is allocated from buddy in page table entry 
modifying
tests. The corresponding tets will be skipped if we fail to allocate 
the

(huge) page. For other test cases, the original page around to kernel
symbol (@start_kernel) is still used.

The patches are organized as below. PATCH[2-10] could be combined to 
one

patch, but it will make the review harder:

   PATCH[1] introduces "struct pgtable_debug_args" as place holder 
of all

    needed information. With it, the old and new implementation
    can coexist.
   PATCH[2-10] uses "struct pgtable_debug_args" in various test 
functions.

   PATCH[11] removes the unused code for old implementation.
   PATCH[12] fixes the issue of corrupted page flag for ARM64

Changelog
=
v6:
    * Populate saved page table entry pointers after
  they're allocated in init_args() (Anshuman)
    * Fix imbalanced preemption count issue by replacing
  pte_alloc_mmap() with pte_alloc() in init_args() (syzbot)


+ vgu...@kernel.org


Please also keep linux-snps-arc CC'ed for ARC changes.



Hello Gavin/Vineet,

This series still need to be tested on ARC ?



Yes, I'm unable to test ARC as it's not supported by QEMU yet.
It would great if Vineet can give it a try on ARC :)


We do have a working QEMU (in the process of being upstreamed) you could try
https://github.com/foss-for-synopsys-dwc-arc-processors/qemu #master

Is this code in some shared git repo we can pull - instead of apply 8 files.

Thx,
-Vineet

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Re: [PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out)

2021-08-13 Thread Vineet Gupta

On 8/12/21 9:01 PM, kernel test robot wrote:

Hi Vineet,

I love your patch! Yet something to improve:

[auto build test ERROR on arc/for-next]
[also build test ERROR on next-20210812]
[cannot apply to linux/master linus/master v5.14-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:https://github.com/0day-ci/linux/commits/Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
base:https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git  for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 10.3.0
reproduce (this is a W=1 build):
 
wgethttps://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross  
-O ~/bin/make.cross
 chmod +x ~/bin/make.cross
 
#https://github.com/0day-ci/linux/commit/0411d3a95cb73722d026f7b3d9c9d8abab8c0d79
 git remote add linux-reviewhttps://github.com/0day-ci/linux
 git fetch --no-tags linux-review 
Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
 git checkout 0411d3a95cb73722d026f7b3d9c9d8abab8c0d79
 # save the attached .config to linux build tree
 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross 
ARCH=arc

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot

All errors (new ones prefixed by >>):

In file included from arch/arc/include/asm/mmu.h:19,
 from include/linux/mm_types.h:19,
 from include/linux/buildid.h:5,
 from include/linux/module.h:14,
 from lib/test_bitops.c:9:

arch/arc/include/asm/mmu-arcv2.h:80:1: error: 'inline' is not at beginning of 
declaration [-Werror=old-style-declaration]

   80 | static void inline mmu_setup_asid(struct mm_struct *mm, unsigned 
long asid)
  | ^~
arch/arc/include/asm/mmu-arcv2.h:85:1: error: 'inline' is not at beginning 
of declaration [-Werror=old-style-declaration]
   85 | static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd)
  | ^~
cc1: all warnings being treated as errors


Strange my gcc11 is not tripping on this snafu. Fixed now.
Thx for the report as always.

-Vineet

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Re: [PATCH v2 08/19] ARC: mm: switch pgtable_t back to struct page *

2021-08-13 Thread Vineet Gupta

On 8/13/21 3:45 AM, kernel test robot wrote:

Hi Vineet,

I love your patch! Yet something to improve:

[auto build test ERROR on arc/for-next]
[also build test ERROR on linux/master linus/master v5.14-rc5 next-20210812]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
base:   https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git for-next
config: arc-randconfig-s032-20210812 (attached as .config)
compiler: arceb-elf-gcc (GCC) 10.3.0
reproduce:
 wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
 chmod +x ~/bin/make.cross
 # apt-get install sparse
 # sparse version: v0.6.3-348-gf0e6938b-dirty
 # 
https://github.com/0day-ci/linux/commit/36e618e081c5a49b2aff51823c5f012045e902ef
 git remote add linux-review https://github.com/0day-ci/linux
 git fetch --no-tags linux-review 
Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
 git checkout 36e618e081c5a49b2aff51823c5f012045e902ef
 # save the attached .config to linux build tree
 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross C=1 
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=arc

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

arch/arc/mm/init.c:35:13: warning: no previous prototype for 
'arc_get_mem_sz' [-Wmissing-prototypes]
   35 | long __init arc_get_mem_sz(void)
  | ^~
arch/arc/mm/init.c:88:13: warning: no previous prototype for 
'setup_arch_memory' [-Wmissing-prototypes]
   88 | void __init setup_arch_memory(void)
  | ^
In file included from :
arch/arc/mm/init.c: In function 'mem_init':

include/linux/compiler_types.h:328:38: error: call to '__compiletime_assert_328' 
declared with attribute error: BUILD_BUG_ON failed: (PTRS_PER_PGD * sizeof(pgd_t)) 
> PAGE_SIZE

  328 |  _compiletime_assert(condition, msg, __compiletime_assert_, 
__COUNTER__)
  |  ^
include/linux/compiler_types.h:309:4: note: in definition of macro 
'__compiletime_assert'
  309 |prefix ## suffix();\
  |^~
include/linux/compiler_types.h:328:2: note: in expansion of macro 
'_compiletime_assert'
  328 |  _compiletime_assert(condition, msg, __compiletime_assert_, 
__COUNTER__)
  |  ^~~
include/linux/build_bug.h:39:37: note: in expansion of macro 
'compiletime_assert'
   39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
  | ^~
include/linux/build_bug.h:50:2: note: in expansion of macro 
'BUILD_BUG_ON_MSG'
   50 |  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  |  ^~~~
arch/arc/mm/init.c:193:2: note: in expansion of macro 'BUILD_BUG_ON'
  193 |  BUILD_BUG_ON((PTRS_PER_PGD * sizeof(pgd_t)) > PAGE_SIZE);
  |  ^~~~



Thx for the report. This is 4K page config, where PGDIR_SHIFT 21 causes 
32-21 = 11 bits or 2k entries which won't fit in 4k page.

I've added the fix and added Tested-by.

-Vineet

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[PATCH v2 17/19] ARC: mm: support 4 levels of page tables

2021-08-12 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h   | 11 +++
 arch/arc/include/asm/pgalloc.h| 11 +++
 arch/arc/include/asm/pgtable-levels.h | 45 ---
 arch/arc/mm/fault.c   |  2 ++
 arch/arc/mm/init.c|  1 +
 arch/arc/mm/tlbex.S   |  9 ++
 6 files changed, 74 insertions(+), 5 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 5d7899d87c08..9a62e1d87967 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
 #define pgd_val(x) ((x).pgd)
 #define __pgd(x)   ((pgd_t) { (x) })
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+typedef struct {
+   unsigned long pud;
+} pud_t;
+
+#define pud_val(x) ((x).pud)
+#define __pud(x)   ((pud_t) { (x) })
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
 typedef struct {
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 781620d2e86f..096b8ef58edb 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -70,6 +70,17 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
return ret;
 }
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
+{
+   set_p4d(p4dp, __p4d((unsigned long)pudp));
+}
+
+#define __pud_free_tlb(tlb, pmd, addr)  pud_free((tlb)->mm, pmd)
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 1c2f022d4ad0..2da3c4e52a91 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -44,8 +44,13 @@
 /*
  * A default 3 level paging testing setup in software walked MMU
  *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ * A default 4 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <3> : <4> : <8> : <13>
  */
 #define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 3
+#define PUD_SHIFT  25
+#endif
 #if CONFIG_PGTABLE_LEVELS > 2
 #define PMD_SHIFT  21
 #endif
@@ -56,17 +61,25 @@
 #define PGDIR_MASK (~(PGDIR_SIZE - 1))
 #define PTRS_PER_PGD   BIT(32 - PGDIR_SHIFT)
 
+#if CONFIG_PGTABLE_LEVELS > 3
+#define PUD_SIZE   BIT(PUD_SHIFT)
+#define PUD_MASK   (~(PUD_SIZE - 1))
+#define PTRS_PER_PUD   BIT(PGDIR_SHIFT - PUD_SHIFT)
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 #define PMD_SIZE   BIT(PMD_SHIFT)
 #define PMD_MASK   (~(PMD_SIZE - 1))
-#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)
+#define PTRS_PER_PMD   BIT(PUD_SHIFT - PMD_SHIFT)
 #endif
 
 #define PTRS_PER_PTE   BIT(PMD_SHIFT - PAGE_SHIFT)
 
 #ifndef __ASSEMBLY__
 
-#if CONFIG_PGTABLE_LEVELS > 2
+#if CONFIG_PGTABLE_LEVELS > 3
+#include 
+#elif CONFIG_PGTABLE_LEVELS > 2
 #include 
 #else
 #include 
@@ -81,9 +94,31 @@
 #define pgd_ERROR(e) \
pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+/* In 4 level paging, p4d_* macros work on pgd */
+#define p4d_none(x)(!p4d_val(x))
+#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
+#define p4d_present(x) (p4d_val(x))
+#define p4d_clear(xp)  do { p4d_val(*(xp)) = 0; } while (0)
+#define p4d_pgtable(p4d)   ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
+#define p4d_page(p4d)  virt_to_page(p4d_pgtable(p4d))
+#define set_p4d(p4dp, p4d) (*(p4dp) = p4d)
+
+/*
+ * 2nd level paging: pud
+ */
+#define pud_ERROR(e) \
+   pr_crit("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
-/* In 3 level paging, pud_* macros work on pgd */
+/*
+ * In 3 level paging, pud_* macros work on pgd
+ * In 4 level paging, pud_* macros work on pud
+ */
 #define pud_none(x)(!pud_val(x))
 #define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
 #define pud_present(x) (pud_val(x))
@@ -93,7 +128,7 @@
 #define set_pud(pudp, pud) (*(pudp) = pud)
 
 /*
- * 2nd level paging: pmd
+ * 3rd level paging: pmd
  */
 #define pmd_ERROR(e) \
pr_crit("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
@@ -121,7 +156,7 @@
 #define pmd_pgtable(pmd)   ((pgtable_t) pmd_page_vaddr(pmd))
 
 /*
- * 3rd level paging: pte
+ * 4th level paging: pte
  */
 #define pte_ERROR(e) \
pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 8da2f0ad8c69..f8994164fa36 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -46,6 +46,8 @@ noinline static int handle_kernel_vaddr_fault(uns

[PATCH v2 14/19] ARC: mm: disintegrate pgtable.h into levels and flags

2021-08-12 Thread Vineet Gupta
 - pgtable-bits-arcv2.h (MMU specific page table flags)
 - pgtable-levels.h (paging levels)

No functional changes, but paves way for easy addition of new MMU code
with different bits and levels etc

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgtable-bits-arcv2.h | 149 
 arch/arc/include/asm/pgtable-levels.h |  91 +++
 arch/arc/include/asm/pgtable.h| 277 +-
 3 files changed, 244 insertions(+), 273 deletions(-)
 create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-levels.h

diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h 
b/arch/arc/include/asm/pgtable-bits-arcv2.h
new file mode 100644
index ..183d23bc1e00
--- /dev/null
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
+ */
+
+/*
+ * page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
+ * There correspond to the corresponding bits in the TLB
+ */
+
+#ifndef _ASM_ARC_PGTABLE_BITS_ARCV2_H
+#define _ASM_ARC_PGTABLE_BITS_ARCV2_H
+
+#ifdef CONFIG_ARC_CACHE_PAGES
+#define _PAGE_CACHEABLE(1 << 0)  /* Cached (H) */
+#else
+#define _PAGE_CACHEABLE0
+#endif
+
+#define _PAGE_EXECUTE  (1 << 1)  /* User Execute  (H) */
+#define _PAGE_WRITE(1 << 2)  /* User Write(H) */
+#define _PAGE_READ (1 << 3)  /* User Read (H) */
+#define _PAGE_ACCESSED (1 << 4)  /* Accessed  (s) */
+#define _PAGE_DIRTY(1 << 5)  /* Modified  (s) */
+#define _PAGE_SPECIAL  (1 << 6)
+#define _PAGE_GLOBAL   (1 << 8)  /* ASID agnostic (H) */
+#define _PAGE_PRESENT  (1 << 9)  /* PTE/TLB Valid (H) */
+
+#ifdef CONFIG_ARC_MMU_V4
+#define _PAGE_HW_SZ(1 << 10)  /* Normal/super (H) */
+#else
+#define _PAGE_HW_SZ0
+#endif
+
+/* Defaults for every user page */
+#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
+
+/* Set of bits not changed in pte_modify */
+#define _PAGE_CHG_MASK (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
+  _PAGE_SPECIAL)
+
+/* More Abbrevaited helpers */
+#define PAGE_U_NONE __pgprot(___DEF)
+#define PAGE_U_R__pgprot(___DEF | _PAGE_READ)
+#define PAGE_U_W_R  __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
+#define PAGE_U_X_R  __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
+#define PAGE_U_X_W_R__pgprot(___DEF \
+   | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
+#define PAGE_KERNEL __pgprot(___DEF | _PAGE_GLOBAL \
+   | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
+
+#define PAGE_SHAREDPAGE_U_W_R
+
+#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
+
+/*
+ * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
+ *
+ * Certain cases have 1:1 mapping
+ *  e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
+ *   which directly corresponds to  PAGE_U_X_R
+ *
+ * Other rules which cause the divergence from 1:1 mapping
+ *
+ *  1. Although ARC700 can do exclusive execute/write protection (meaning R
+ * can be tracked independet of X/W unlike some other CPUs), still to
+ * keep things consistent with other archs:
+ *  -Write implies Read:   W => R
+ *  -Execute implies Read: X => R
+ *
+ *  2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
+ * This is to enable COW mechanism
+ */
+   /* xwr */
+#define __P000  PAGE_U_NONE
+#define __P001  PAGE_U_R
+#define __P010  PAGE_U_R   /* Pvt-W => !W */
+#define __P011  PAGE_U_R   /* Pvt-W => !W */
+#define __P100  PAGE_U_X_R /* X => R */
+#define __P101  PAGE_U_X_R
+#define __P110  PAGE_U_X_R /* Pvt-W => !W and X => R */
+#define __P111  PAGE_U_X_R /* Pvt-W => !W */
+
+#define __S000  PAGE_U_NONE
+#define __S001  PAGE_U_R
+#define __S010  PAGE_U_W_R /* W => R */
+#define __S011  PAGE_U_W_R
+#define __S100  PAGE_U_X_R /* X => R */
+#define __S101  PAGE_U_X_R
+#define __S110  PAGE_U_X_W_R   /* X => R */
+#define __S111  PAGE_U_X_W_R
+
+#ifndef __ASSEMBLY__
+
+#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
+#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
+#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
+#define pte_special(pte)   (pte_val(pte) & _PAGE_SPECIAL)
+
+#define PTE_BIT_FUNC(fn, op) \
+   static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+PTE_BIT_FUNC(mknotpresent, &= ~(_PAGE_PRESENT));
+PTE_BIT_FUNC(wrprotect,&= ~(_PAGE_WRITE));
+PTE_BIT_FUNC(mkwrite,  |= (_PAGE_WRITE));
+PTE_BIT_FUNC(mkclean,  &= ~(_PAGE_DIRTY));
+PTE_BIT_FUNC(mkdirty,  |= (_PA

[PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out)

2021-08-12 Thread Vineet Gupta
non functional change

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/mmu-arcv2.h | 103 +++
 arch/arc/include/asm/mmu.h   |  80 +---
 arch/arc/include/asm/pgtable.h   |   6 --
 3 files changed, 105 insertions(+), 84 deletions(-)
 create mode 100644 arch/arc/include/asm/mmu-arcv2.h

diff --git a/arch/arc/include/asm/mmu-arcv2.h b/arch/arc/include/asm/mmu-arcv2.h
new file mode 100644
index ..4c47dd3864d1
--- /dev/null
+++ b/arch/arc/include/asm/mmu-arcv2.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. 
(www.synopsys.com)
+ *
+ * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software 
managed.
+ * This file contains the TLB access registers and commands
+ */
+
+#ifndef _ASM_ARC_MMU_ARCV2_H
+#define _ASM_ARC_MMU_ARCV2_H
+
+/*
+ * TLB Management regs
+ */
+#define ARC_REG_MMU_BCR0x06f
+
+#ifdef CONFIG_ARC_MMU_V3
+#define ARC_REG_TLBPD0 0x405
+#define ARC_REG_TLBPD1 0x406
+#define ARC_REG_TLBPD1HI   0   /* Dummy: allows common code */
+#define ARC_REG_TLBINDEX   0x407
+#define ARC_REG_TLBCOMMAND 0x408
+#define ARC_REG_PID0x409
+#define ARC_REG_SCRATCH_DATA0  0x418
+#else
+#define ARC_REG_TLBPD0 0x460
+#define ARC_REG_TLBPD1 0x461
+#define ARC_REG_TLBPD1HI   0x463
+#define ARC_REG_TLBINDEX   0x464
+#define ARC_REG_TLBCOMMAND 0x465
+#define ARC_REG_PID0x468
+#define ARC_REG_SCRATCH_DATA0  0x46c
+#endif
+
+/* Bits in MMU PID reg */
+#define __TLB_ENABLE   (1 << 31)
+#define __PROG_ENABLE  (1 << 30)
+#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
+
+/* Bits in TLB Index reg */
+#define TLB_LKUP_ERR   0x8000
+
+#ifdef CONFIG_ARC_MMU_V3
+#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x0001)
+#else
+#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x4000)
+#endif
+
+/*
+ * TLB Commands
+ */
+#define TLBWrite   0x1
+#define TLBRead0x2
+#define TLBGetIndex0x3
+#define TLBProbe   0x4
+#define TLBWriteNI 0x5  /* write JTLB without inv uTLBs */
+#define TLBIVUTLB  0x6  /* explicitly inv uTLBs */
+
+#ifdef CONFIG_ARC_MMU_V4
+#define TLBInsertEntry 0x7
+#define TLBDeleteEntry 0x8
+#endif
+
+/* Masks for actual TLB "PD"s */
+#define PTE_BITS_IN_PD0(_PAGE_GLOBAL | _PAGE_PRESENT | 
_PAGE_HW_SZ)
+#define PTE_BITS_RWX   (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
+
+#define PTE_BITS_NON_RWX_IN_PD1(PAGE_MASK_PHYS | _PAGE_CACHEABLE)
+
+#ifndef __ASSEMBLY__
+
+struct mm_struct;
+extern int pae40_exist_but_not_enab(void);
+
+static inline int is_pae40_enabled(void)
+{
+   return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
+}
+
+static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
+{
+   write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
+}
+
+static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd)
+{
+   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
+#ifdef CONFIG_ISA_ARCV2
+   write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
+#endif
+}
+
+#else
+
+.macro ARC_MMU_REENABLE reg
+   lr \reg, [ARC_REG_PID]
+   or \reg, \reg, MMU_ENABLE
+   sr \reg, [ARC_REG_PID]
+.endm
+
+#endif /* !__ASSEMBLY__ */
+
+#endif
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 414a27e806b6..ca427c30f70e 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -7,91 +7,15 @@
 #define _ASM_ARC_MMU_H
 
 #ifndef __ASSEMBLY__
-#include  /* NR_CPUS */
-#endif
-
-/* MMU Management regs */
-#define ARC_REG_MMU_BCR0x06f
-
-#ifdef CONFIG_ARC_MMU_V3
-#define ARC_REG_TLBPD0 0x405
-#define ARC_REG_TLBPD1 0x406
-#define ARC_REG_TLBPD1HI   0   /* Dummy: allows code sharing with 
ARC700 */
-#define ARC_REG_TLBINDEX   0x407
-#define ARC_REG_TLBCOMMAND 0x408
-#define ARC_REG_PID0x409
-#define ARC_REG_SCRATCH_DATA0  0x418
-#else
-#define ARC_REG_TLBPD0 0x460
-#define ARC_REG_TLBPD1 0x461
-#define ARC_REG_TLBPD1HI   0x463
-#define ARC_REG_TLBINDEX   0x464
-#define ARC_REG_TLBCOMMAND 0x465
-#define ARC_REG_PID0x468
-#define ARC_REG_SCRATCH_DATA0  0x46c
-#endif
-
-/* Bits in MMU PID register */
-#define __TLB_ENABLE   (1 << 31)
-#define __PROG_ENABLE  (1 << 30)
-#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
-
-/* Error code if probe fails */
-#define TLB_LKUP_ERR   0x8000
-
-#ifdef CONFIG_ARC_MMU_V3
-#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x0001)
-#else
-#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x4000)
-#endif
-
-/* TLB Commands */
-#define TLBWrite0x1
-#define TLBRead 0x2
-#define TLBGetIndex 0x3
-#define 

[PATCH v2 12/19] ARC: mm: move MMU specific bits out of entry code ...

2021-08-12 Thread Vineet Gupta
... to avoid polluting shared entry code (across three ISA variants)
with ISA/MMU specific code.

Cc: Jose Abreu 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/mmu.h| 8 
 arch/arc/kernel/entry-arcv2.S | 1 +
 arch/arc/kernel/entry.S   | 7 ++-
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 0b117ea07048..414a27e806b6 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -84,6 +84,14 @@ static inline int is_pae40_enabled(void)
 
 extern int pae40_exist_but_not_enab(void);
 
+#else
+
+.macro ARC_MMU_REENABLE reg
+   lr \reg, [ARC_REG_PID]
+   or \reg, \reg, MMU_ENABLE
+   sr \reg, [ARC_REG_PID]
+.endm
+
 #endif /* !__ASSEMBLY__ */
 
 #endif
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index 12d5f12d10d2..a7e6a2174187 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 ; A maximum number of supported interrupts in the core interrupt controller.
 ; This number is not equal to the maximum interrupt number (256) because
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 2cb8dfe866b6..dd77a0c8f740 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -101,11 +101,8 @@ ENTRY(EV_MachineCheck)
lr  r0, [efa]
mov r1, sp
 
-   ; hardware auto-disables MMU, re-enable it to allow kernel vaddr
-   ; access for say stack unwinding of modules for crash dumps
-   lr  r3, [ARC_REG_PID]
-   or  r3, r3, MMU_ENABLE
-   sr  r3, [ARC_REG_PID]
+   ; MC excpetions disable MMU
+   ARC_MMU_REENABLE r3
 
lsr r3, r2, 8
bmskr3, r3, 7
-- 
2.25.1


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[PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code

2021-08-12 Thread Vineet Gupta
PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-*
but only for !__ASSEMBLY__

tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs
for CONFIG_PGTABLE_LEVEL={2,3} and works for 4.

So add a workaround local to tlbex.S - the proper fix is to change
asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too

Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/tlbex.S | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 0b4bb62fa0ab..c4a5f16444ce 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -145,6 +145,14 @@ ex_saved_reg1:
 ;TLB Miss handling Code
 ;
 
+#ifndef PMD_SHIFT
+#define PMD_SHIFT PUD_SHIFT
+#endif
+
+#ifndef PUD_SHIFT
+#define PUD_SHIFT PGDIR_SHIFT
+#endif
+
 ;-
 ; This macro does the page-table lookup for the faulting address.
 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
-- 
2.25.1


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[PATCH v2 19/19] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd, pud, pmd entries

2021-08-12 Thread Vineet Gupta
ARCv3 hardware walker expects Table Descriptors to have b'11 in LSB bits
to continue moving to next level.

This commits adds that (to ARCv2 code) and ensures that it works in
software walked regime.

The pte entries stil need tagging, but that is not possible in ARCv2
since the LSB 2 bits are currently used.

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgalloc.h| 8 
 arch/arc/include/asm/pgtable-bits-arcv2.h | 2 ++
 arch/arc/include/asm/pgtable-levels.h | 6 +++---
 arch/arc/mm/tlbex.S   | 4 +++-
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 096b8ef58edb..a8c01eceba1b 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -43,12 +43,12 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t 
*pte)
 *
 * The cast itself is needed given simplistic definition of set_pmd()
 */
-   set_pmd(pmd, __pmd((unsigned long)pte));
+   set_pmd(pmd, __pmd((unsigned long)pte | _PAGE_TABLE));
 }
 
 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t 
pte_page)
 {
-   set_pmd(pmd, __pmd((unsigned long)page_address(pte_page)));
+   set_pmd(pmd, __pmd((unsigned long)page_address(pte_page) | 
_PAGE_TABLE));
 }
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
@@ -74,7 +74,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 
 static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
 {
-   set_p4d(p4dp, __p4d((unsigned long)pudp));
+   set_p4d(p4dp, __p4d((unsigned long)pudp | _PAGE_TABLE));
 }
 
 #define __pud_free_tlb(tlb, pmd, addr)  pud_free((tlb)->mm, pmd)
@@ -85,7 +85,7 @@ static inline void p4d_populate(struct mm_struct *mm, p4d_t 
*p4dp, pud_t *pudp)
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
 {
-   set_pud(pudp, __pud((unsigned long)pmdp));
+   set_pud(pudp, __pud((unsigned long)pmdp | _PAGE_TABLE));
 }
 
 #define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h 
b/arch/arc/include/asm/pgtable-bits-arcv2.h
index 183d23bc1e00..54aba0d3ae34 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -32,6 +32,8 @@
 #define _PAGE_HW_SZ0
 #endif
 
+#define _PAGE_TABLE0x3
+
 /* Defaults for every user page */
 #define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
 
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 2da3c4e52a91..6c7a8360d986 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -98,7 +98,7 @@
 
 /* In 4 level paging, p4d_* macros work on pgd */
 #define p4d_none(x)(!p4d_val(x))
-#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
+#define p4d_bad(x) (!(p4d_val(x) & _PAGE_TABLE))
 #define p4d_present(x) (p4d_val(x))
 #define p4d_clear(xp)  do { p4d_val(*(xp)) = 0; } while (0)
 #define p4d_pgtable(p4d)   ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
@@ -120,7 +120,7 @@
  * In 4 level paging, pud_* macros work on pud
  */
 #define pud_none(x)(!pud_val(x))
-#define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
+#define pud_bad(x) (!(pud_val(x) & _PAGE_TABLE))
 #define pud_present(x) (pud_val(x))
 #define pud_clear(xp)  do { pud_val(*(xp)) = 0; } while (0)
 #define pud_pgtable(pud)   ((pmd_t *)(pud_val(pud) & PAGE_MASK))
@@ -147,7 +147,7 @@
  * In 3+ level paging (pgd -> pmd -> pte), pmd_* macros work on pmd
  */
 #define pmd_none(x)(!pmd_val(x))
-#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
+#define pmd_bad(pmd)   (!(pmd_val(pmd) & _PAGE_TABLE))
 #define pmd_present(x) (pmd_val(x))
 #define pmd_clear(xp)  do { pmd_val(*(xp)) = 0; } while (0)
 #define pmd_page_vaddr(pmd)(pmd_val(pmd) & PAGE_MASK)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index e054780a8fe0..3874a8086591 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -171,11 +171,12 @@ ex_saved_reg1:
lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
ld.as   r3, [r1, r0]; PGD entry corresp to faulting addr
tst r3, r3
-   bz  do_slow_path_pf ; if no Page Table, do page fault
+   bz  do_slow_path_pf ; next level table missing, handover to 
linux vm code
 
 #if CONFIG_PGTABLE_LEVELS > 3
lsr r0, r2, PUD_SHIFT   ; Bits for indexing into PUD
and r0, r0, (PTRS_PER_PUD - 1)
+   bmskn   r3, r3, 1   ; clear _PAGE_TABLE bits
ld.as   r1, [r3, r0]; PMD entry
tst r1, r1
bz  do_slow_path_pf
@@ -185,6 +186,7 @@ ex_saved_reg1:
 #if CONFIG_P

[PATCH v2 03/19] ARC: mm: move mmu/cache externs out to setup.h

2021-08-12 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/cache.h |  4 
 arch/arc/include/asm/mmu.h   |  4 
 arch/arc/include/asm/setup.h | 12 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d8ece4292388..f0f1fc5d62b6 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -62,10 +62,6 @@
 #define ARCH_SLAB_MINALIGN 8
 #endif
 
-extern void arc_cache_init(void);
-extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
-extern void read_decode_cache_bcr(void);
-
 extern int ioc_enable;
 extern unsigned long perip_base, perip_end;
 
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 38a036508699..762cfe66e16b 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,10 +64,6 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
-void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-void read_decode_mmu_bcr(void);
-
 static inline int is_pae40_enabled(void)
 {
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h
index 01f85478170d..028a8cf76206 100644
--- a/arch/arc/include/asm/setup.h
+++ b/arch/arc/include/asm/setup.h
@@ -2,8 +2,8 @@
 /*
  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  */
-#ifndef __ASMARC_SETUP_H
-#define __ASMARC_SETUP_H
+#ifndef __ASM_ARC_SETUP_H
+#define __ASM_ARC_SETUP_H
 
 
 #include 
@@ -34,4 +34,12 @@ long __init arc_get_mem_sz(void);
 #define IS_AVAIL2(v, s, cfg)   IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg))
 #define IS_AVAIL3(v, v2, s)IS_AVAIL1(v, s), IS_AVAIL1(v, 
IS_DISABLED_RUN(v2))
 
+extern void arc_mmu_init(void);
+extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
+extern void read_decode_mmu_bcr(void);
+
+extern void arc_cache_init(void);
+extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
+extern void read_decode_cache_bcr(void);
+
 #endif /* __ASMARC_SETUP_H */
-- 
2.25.1


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[PATCH v2 10/19] ARC: mm: non-functional code cleanup ahead of 3 levels

2021-08-12 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h | 30 --
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 514b8b70df50..28ed82b1800f 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -34,6 +34,13 @@ void copy_user_highpage(struct page *to, struct page *from,
unsigned long u_vaddr, struct vm_area_struct *vma);
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
 
+typedef struct {
+   unsigned long pgd;
+} pgd_t;
+
+#define pgd_val(x) ((x).pgd)
+#define __pgd(x)   ((pgd_t) { (x) })
+
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
@@ -41,22 +48,17 @@ typedef struct {
unsigned long pte;
 #endif
 } pte_t;
-typedef struct {
-   unsigned long pgd;
-} pgd_t;
+
+#define pte_val(x) ((x).pte)
+#define __pte(x)   ((pte_t) { (x) })
+
 typedef struct {
unsigned long pgprot;
 } pgprot_t;
 
-#define pte_val(x)  ((x).pte)
-#define pgd_val(x)  ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)((pte_t) { (x) })
-#define __pgd(x)((pgd_t) { (x) })
-#define __pgprot(x) ((pgprot_t) { (x) })
-
-#define pte_pgprot(x) __pgprot(pte_val(x))
+#define pgprot_val(x)  ((x).pgprot)
+#define __pgprot(x)((pgprot_t) { (x) })
+#define pte_pgprot(x)  __pgprot(pte_val(x))
 
 typedef struct page *pgtable_t;
 
@@ -96,8 +98,8 @@ extern int pfn_valid(unsigned long pfn);
  * virt here means link-address/program-address as embedded in object code.
  * And for ARC, link-addr = physical address
  */
-#define __pa(vaddr)  ((unsigned long)(vaddr))
-#define __va(paddr)  ((void *)((unsigned long)(paddr)))
+#define __pa(vaddr)((unsigned long)(vaddr))
+#define __va(paddr)((void *)((unsigned long)(paddr)))
 
 #define virt_to_page(kaddr)pfn_to_page(virt_to_pfn(kaddr))
 #define virt_addr_valid(kaddr)  pfn_valid(virt_to_pfn(kaddr))
-- 
2.25.1


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[PATCH v2 16/19] ARC: mm: support 3 levels of page tables

2021-08-12 Thread Vineet Gupta
ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
Forthcoming hw will have multiple levels, so this change preps mm code
for same. It is also fun to try multi levels even on soft-walked code to
ensure generic mm code is robust to handle.

overview


2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on 
pgd
3 levels {pgd, pmd, pte}:
  - pud is folded and pud_* macros point to pgd
  - pmd_* macros operate on actual pmd

code changes


1. #include 

2. Define CONFIG_PGTABLE_LEVELS 3

3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t
3b. Define pmd_val() which actually deals with pmd
(pmd_offset(), pmd_index() are provided by generic code)
3c. pmd_alloc_one()/pmd_free() also provided by generic code
(pmd_populate/pmd_free already exist)

4. Define pud_none(), pud_bad() macros based on generic pud_val() which
   internally pertains to pgd now.
4b. define pud_populate() to just setup pgd

Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig  |  4 ++
 arch/arc/include/asm/page.h   | 11 +
 arch/arc/include/asm/pgalloc.h| 11 +
 arch/arc/include/asm/pgtable-levels.h | 63 ---
 arch/arc/include/asm/processor.h  |  2 +-
 arch/arc/mm/fault.c   |  4 ++
 arch/arc/mm/init.c|  1 +
 arch/arc/mm/tlb.c |  4 +-
 arch/arc/mm/tlbex.S   |  9 
 9 files changed, 101 insertions(+), 8 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 59d5b2a179f6..43cb8aaf57a2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -314,6 +314,10 @@ config ARC_HUGEPAGE_16M
 
 endchoice
 
+config PGTABLE_LEVELS
+   int "Number of Page table levels"
+   default 2
+
 config ARC_COMPACT_IRQ_LEVELS
depends on ISA_ARCOMPACT
bool "Setup Timer IRQ as high Priority"
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 28ed82b1800f..5d7899d87c08 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
 #define pgd_val(x) ((x).pgd)
 #define __pgd(x)   ((pgd_t) { (x) })
 
+#if CONFIG_PGTABLE_LEVELS > 2
+
+typedef struct {
+   unsigned long pmd;
+} pmd_t;
+
+#define pmd_val(x) ((x).pmd)
+#define __pmd(x)   ((pmd_t) { (x) })
+
+#endif
+
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 0cde9e5eefd7..781620d2e86f 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -70,6 +70,17 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
return ret;
 }
 
+#if CONFIG_PGTABLE_LEVELS > 2
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
+{
+   set_pud(pudp, __pud((unsigned long)pmdp));
+}
+
+#define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
+
+#endif
+
 #define __pte_free_tlb(tlb, pte, addr)  pte_free((tlb)->mm, pte)
 
 #endif /* _ASM_ARC_PGALLOC_H */
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 8ece75335bb5..1c2f022d4ad0 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -10,6 +10,8 @@
 #ifndef _ASM_ARC_PGTABLE_LEVELS_H
 #define _ASM_ARC_PGTABLE_LEVELS_H
 
+#if CONFIG_PGTABLE_LEVELS == 2
+
 /*
  * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
  *
@@ -37,16 +39,38 @@
 #define PGDIR_SHIFT21
 #endif
 
-#define PGDIR_SIZE BIT(PGDIR_SHIFT)/* vaddr span, not PDG 
sz */
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+#else
+
+/*
+ * A default 3 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ */
+#define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SHIFT  21
+#endif
+
+#endif
 
+#define PGDIR_SIZE BIT(PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
 #define PTRS_PER_PGD   BIT(32 - PGDIR_SHIFT)
 
-#define PTRS_PER_PTE   BIT(PGDIR_SHIFT - PAGE_SHIFT)
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SIZE   BIT(PMD_SHIFT)
+#define PMD_MASK   (~(PMD_SIZE - 1))
+#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)
+#endif
+
+#define PTRS_PER_PTE   BIT(PMD_SHIFT - PAGE_SHIFT)
 
 #ifndef __ASSEMBLY__
 
+#if CONFIG_PGTABLE_LEVELS > 2
+#include 
+#else
 #include 
+#endif
 
 /*
  * 1st level paging: pgd
@@ -57,9 +81,35 @@
 #define pgd_ERROR(e) \
pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
+#if CONFIG_PGTABLE_LEVELS > 2
+
+/* In 3 level paging, pud_* macros work on pgd */
+#define pud_none(x)(!pud_val(x))
+#define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
+#define pud_prese

[PATCH v2 08/19] ARC: mm: switch pgtable_t back to struct page *

2021-08-12 Thread Vineet Gupta
So far ARC pgtable_t has not been struct page based to avoid extra
page_address() calls involved. However the differences are down to
noise and get in the way of using generic code, hence this patch.

Suggested-by: Mike Rapoport 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h|  2 +-
 arch/arc/include/asm/pgalloc.h | 57 ++
 arch/arc/mm/init.c |  3 ++
 3 files changed, 21 insertions(+), 41 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index c4ac827379cd..514b8b70df50 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -58,7 +58,7 @@ typedef struct {
 
 #define pte_pgprot(x) __pgprot(pte_val(x))
 
-typedef pte_t * pgtable_t;
+typedef struct page *pgtable_t;
 
 /*
  * Use virt_to_pfn with caution:
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 408bc4b0842d..8ab1af3da6e7 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -45,22 +45,17 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t 
*pte)
set_pmd(pmd, __pmd((unsigned long)pte));
 }
 
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t 
pte)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t 
pte_page)
 {
-   set_pmd(pmd, __pmd((unsigned long)pte));
-}
-
-static inline int __get_order_pgd(void)
-{
-   return get_order(PTRS_PER_PGD * sizeof(pgd_t));
+   set_pmd(pmd, __pmd((unsigned long)page_address(pte_page)));
 }
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-   int num, num2;
-   pgd_t *ret = (pgd_t *) __get_free_pages(GFP_KERNEL, __get_order_pgd());
+   pgd_t *ret = (pgd_t *) __get_free_page(GFP_KERNEL);
 
if (ret) {
+   int num, num2;
num = USER_PTRS_PER_PGD + USER_KERNEL_GUTTER / PGDIR_SIZE;
memzero(ret, num * sizeof(pgd_t));
 
@@ -76,61 +71,43 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 
 static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 {
-   free_pages((unsigned long)pgd, __get_order_pgd());
-}
-
-
-/*
- * With software-only page-tables, addr-split for traversal is tweakable and
- * that directly governs how big tables would be at each level.
- * Further, the MMU page size is configurable.
- * Thus we need to programatically assert the size constraint
- * All of this is const math, allowing gcc to do constant folding/propagation.
- */
-
-static inline int __get_order_pte(void)
-{
-   return get_order(PTRS_PER_PTE * sizeof(pte_t));
+   free_page((unsigned long)pgd);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
 {
pte_t *pte;
 
-   pte = (pte_t *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
-__get_order_pte());
+   pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_ZERO);
 
return pte;
 }
 
-static inline pgtable_t
-pte_alloc_one(struct mm_struct *mm)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm)
 {
-   pgtable_t pte_pg;
struct page *page;
 
-   pte_pg = (pgtable_t)__get_free_pages(GFP_KERNEL, __get_order_pte());
-   if (!pte_pg)
-   return 0;
-   memzero((void *)pte_pg, PTRS_PER_PTE * sizeof(pte_t));
-   page = virt_to_page(pte_pg);
+   page = (pgtable_t)alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_ACCOUNT);
+   if (!page)
+   return NULL;
+
if (!pgtable_pte_page_ctor(page)) {
__free_page(page);
-   return 0;
+   return NULL;
}
 
-   return pte_pg;
+   return page;
 }
 
 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
 {
-   free_pages((unsigned long)pte, __get_order_pte()); /* takes phy addr */
+   free_page((unsigned long)pte);
 }
 
-static inline void pte_free(struct mm_struct *mm, pgtable_t ptep)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte_page)
 {
-   pgtable_pte_page_dtor(virt_to_page(ptep));
-   free_pages((unsigned long)ptep, __get_order_pte());
+   pgtable_pte_page_dtor(pte_page);
+   __free_page(pte_page);
 }
 
 #define __pte_free_tlb(tlb, pte, addr)  pte_free((tlb)->mm, pte)
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index c083bf660cec..46ad9aee7a73 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -189,6 +189,9 @@ void __init mem_init(void)
 {
memblock_free_all();
highmem_init();
+
+   BUILD_BUG_ON((PTRS_PER_PGD * sizeof(pgd_t)) > PAGE_SIZE);
+   BUILD_BUG_ON((PTRS_PER_PTE * sizeof(pte_t)) > PAGE_SIZE);
 }
 
 #ifdef CONFIG_HIGHMEM
-- 
2.25.1


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[PATCH v2 18/19] ARC: mm: vmalloc sync from kernel to user table to update PMD ...

2021-08-12 Thread Vineet Gupta
... not PGD

vmalloc() sets up the kernel page table (starting from @swapper_pg_dir).
But when vmalloc area is accessed in context of a user task, say opening
terminal in n_tty_open(), the user page tables need to be synced from
kernel page tables so that TLB entry is created in "user context".

The old code was doing this incorrectly, as it was updating the user pgd
entry (first level itself) to point to kernel pud table (2nd level),
effectively yanking away the entire user space translation with kernel one.

The correct way to do this is to ONLY update a user space pgd/pud/pmd entry
if it is not popluated already. This ensures that only the missing leaf
pmd entry gets updated to point to relevant kernel pte table.

>From code change pov, we are chaging the pattern:

p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
if (!p4d_present(*p4d_k))
goto bad_area;
set_p4d(p4d, *p4d_k);

with
p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
if (p4d_none(*p4d_k))
goto bad_area;
if (!p4d_present(*p4d))
set_p4d(p4d, *p4d_k);

Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/fault.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index f8994164fa36..5787c261c9a4 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -36,31 +36,31 @@ noinline static int handle_kernel_vaddr_fault(unsigned long 
address)
pgd = pgd_offset(current->active_mm, address);
pgd_k = pgd_offset_k(address);
 
-   if (!pgd_present(*pgd_k))
+   if (pgd_none (*pgd_k))
goto bad_area;
-
-   set_pgd(pgd, *pgd_k);
+   if (!pgd_present(*pgd))
+   set_pgd(pgd, *pgd_k);
 
p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
-   if (!p4d_present(*p4d_k))
+   if (p4d_none(*p4d_k))
goto bad_area;
-
-   set_p4d(p4d, *p4d_k);
+   if (!p4d_present(*p4d))
+   set_p4d(p4d, *p4d_k);
 
pud = pud_offset(p4d, address);
pud_k = pud_offset(p4d_k, address);
-   if (!pud_present(*pud_k))
+   if (pud_none(*pud_k))
goto bad_area;
-
-   set_pud(pud, *pud_k);
+   if (!pud_present(*pud))
+   set_pud(pud, *pud_k);
 
pmd = pmd_offset(pud, address);
pmd_k = pmd_offset(pud_k, address);
-   if (!pmd_present(*pmd_k))
+   if (pmd_none(*pmd_k))
goto bad_area;
-
-   set_pmd(pmd, *pmd_k);
+   if (!pmd_present(*pmd))
+   set_pmd(pmd, *pmd_k);
 
/* XXX: create the TLB entry here */
return 0;
-- 
2.25.1


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[PATCH v2 06/19] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

2021-08-12 Thread Vineet Gupta
and remove the one off uncached definition for ARC

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgtable.h | 3 ---
 arch/arc/mm/ioremap.c  | 3 ++-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 80b57c14b430..b054c14f8bf6 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -103,9 +103,6 @@
  */
 #define PAGE_KERNEL  __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE)
 
-/* ioremap */
-#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
-
 /* Masks for actual TLB "PD"s */
 #define PTE_BITS_IN_PD0(_PAGE_GLOBAL | _PAGE_PRESENT | 
_PAGE_HW_SZ)
 #define PTE_BITS_RWX   (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 052bbd8b1e5f..0ee75aca6e10 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -39,7 +39,8 @@ void __iomem *ioremap(phys_addr_t paddr, unsigned long size)
if (arc_uncached_addr_space(paddr))
return (void __iomem *)(u32)paddr;
 
-   return ioremap_prot(paddr, size, pgprot_val(PAGE_KERNEL_NO_CACHE));
+   return ioremap_prot(paddr, size,
+   pgprot_val(pgprot_noncached(PAGE_KERNEL)));
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
2.25.1


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[PATCH v2 04/19] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS

2021-08-12 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/tlb.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 6079dfd129b9..15cbc285b0de 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -71,7 +71,7 @@ static void tlb_entry_erase(unsigned int vaddr_n_asid)
}
 }
 
-static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
+static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
 {
unsigned int idx;
 
@@ -109,13 +109,16 @@ static void tlb_entry_erase(unsigned int vaddr_n_asid)
write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
 }
 
-static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
+static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
 {
write_aux_reg(ARC_REG_TLBPD0, pd0);
-   write_aux_reg(ARC_REG_TLBPD1, pd1);
 
-   if (is_pae40_enabled())
+   if (!is_pae40_enabled()) {
+   write_aux_reg(ARC_REG_TLBPD1, pd1);
+   } else {
+   write_aux_reg(ARC_REG_TLBPD1, pd1 & 0x);
write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
+   }
 
write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
 }
@@ -391,7 +394,7 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
unsigned long flags;
unsigned int asid_or_sasid, rwx;
unsigned long pd0;
-   pte_t pd1;
+   phys_addr_t pd1;
 
/*
 * create_tlb() assumes that current->mm == vma->mm, since
-- 
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[PATCH v2 11/19] ARC: mm: move MMU specific bits out of ASID allocator

2021-08-12 Thread Vineet Gupta
And while at it, rewrite commentary on ASID allocator

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/mmu.h | 13 +
 arch/arc/include/asm/mmu_context.h | 28 +---
 arch/arc/mm/tlb.c  | 11 ---
 3 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 762cfe66e16b..0b117ea07048 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,6 +64,19 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
+static void inline mmu_setup_asid(struct mm_struct *mm, unsigned int asid)
+{
+   write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
+}
+
+static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd)
+{
+   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
+#ifdef CONFIG_ISA_ARCV2
+   write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
+#endif
+}
+
 static inline int is_pae40_enabled(void)
 {
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
diff --git a/arch/arc/include/asm/mmu_context.h 
b/arch/arc/include/asm/mmu_context.h
index 49318a126879..dda471f5f05b 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -15,22 +15,23 @@
 #ifndef _ASM_ARC_MMU_CONTEXT_H
 #define _ASM_ARC_MMU_CONTEXT_H
 
-#include 
-#include 
 #include 
 
+#include 
 #include 
 
-/* ARC700 ASID Management
+/* ARC ASID Management
+ *
+ * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
+ * context-switch.
  *
- * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
- * with same vaddr (different tasks) to co-exit. This provides for
- * "Fast Context Switch" i.e. no TLB flush on ctxt-switch
+ * ASID is managed per cpu, so task threads across CPUs can have different
+ * ASID. Global ASID management is needed if hardware supports TLB shootdown
+ * and/or shared TLB across cores, which ARC doesn't.
  *
- * Linux assigns each task a unique ASID. A simple round-robin allocation
- * of H/w ASID is done using software tracker @asid_cpu.
- * When it reaches max 255, the allocation cycle starts afresh by flushing
- * the entire TLB and wrapping ASID back to zero.
+ * Each task is assigned unique ASID, with a simple round-robin allocator
+ * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started
+ * over from 0, and TLB is flushed
  *
  * A new allocation cycle, post rollover, could potentially reassign an ASID
  * to a different task. Thus the rule is to refresh the ASID in a new cycle.
@@ -93,7 +94,7 @@ static inline void get_new_mmu_context(struct mm_struct *mm)
asid_mm(mm, cpu) = asid_cpu(cpu);
 
 set_hw:
-   write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE);
+   mmu_setup_asid(mm, hw_pid(mm, cpu));
 
local_irq_restore(flags);
 }
@@ -146,10 +147,7 @@ static inline void switch_mm(struct mm_struct *prev, 
struct mm_struct *next,
 */
cpumask_set_cpu(cpu, mm_cpumask(next));
 
-#ifdef CONFIG_ISA_ARCV2
-   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
-   write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
-#endif
+   mmu_setup_pgd(next, next->pgd);
 
get_new_mmu_context(next);
 }
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 15cbc285b0de..b68d5798327b 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -716,14 +716,11 @@ void arc_mmu_init(void)
if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
panic("Hardware doesn't support PAE40\n");
 
-   /* Enable the MMU */
-   write_aux_reg(ARC_REG_PID, MMU_ENABLE);
+   /* Enable the MMU with ASID 0 */
+   mmu_setup_asid(NULL, 0);
 
-   /* In arc700/smp needed for re-entrant interrupt handling */
-#ifdef CONFIG_ISA_ARCV2
-   /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
-   write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
-#endif
+   /* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */
+   mmu_setup_pgd(NULL, swapper_pg_dir);
 
if (pae40_exist_but_not_enab())
write_aux_reg(ARC_REG_TLBPD1HI, 0);
-- 
2.25.1


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[PATCH v2 07/19] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)

2021-08-12 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgalloc.h | 14 ++
 arch/arc/include/asm/pgtable.h |  6 --
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index a32ca3104ced..408bc4b0842d 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -35,13 +35,19 @@
 static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
 {
-   pmd_set(pmd, pte);
+   /*
+* The cast to long below is OK in 32-bit PAE40 regime with long long 
pte
+* Despite "wider" pte, the pte table needs to be in non-PAE low memory
+* as all higher levels can only hold long pointers.
+*
+* The cast itself is needed given simplistic definition of set_pmd()
+*/
+   set_pmd(pmd, __pmd((unsigned long)pte));
 }
 
-static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t ptep)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t 
pte)
 {
-   pmd_set(pmd, (pte_t *) ptep);
+   set_pmd(pmd, __pmd((unsigned long)pte));
 }
 
 static inline int __get_order_pgd(void)
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index b054c14f8bf6..f762bacb2358 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -222,12 +222,6 @@ extern char empty_zero_page[PAGE_SIZE];
 /* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
 #define pmd_page_vaddr(pmd)(pmd_val(pmd) & PAGE_MASK)
 
-/* In a 2 level sys, setup the PGD entry with PTE value */
-static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
-{
-   pmd_val(*pmdp) = (unsigned long)ptep;
-}
-
 #define pte_none(x)(!pte_val(x))
 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
 #define pte_clear(mm, addr, ptep)  set_pte_at(mm, addr, ptep, __pte(0))
-- 
2.25.1


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[PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc

2021-08-12 Thread Vineet Gupta
Hi,

Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from
current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based
cores).

Most of these changes are incremental cleanups to make way for 14/18 and
15/18 which actually imeplement the new levels (in existing ARCv2 port)
and worth a critical eye.

CC'ing some of you guys dealing with page tables for a while :-)
to spot any obvious gotchas.

Thx,
-Vineet

Changes since v1 [1]
 - Switched ARC to asm-generic/pgalloc.h  (so struct page based pgtable_t)  
[Mike Rapoport]
 - Dropped {pud,pmd}_alloc_one/{pud,pmd}_free provided by asm-generic/pgalloc.h 
[Mike Rapoport]
 - Negative diffstat now due to above
 - Added BUILD_BUG_ON() to arch/arc/mm/init.c for sanity of table sizes
 - Consolidated 2 patches related to ARC_USE_SCRATCH_REG
   [Mike Rapoport]
 - Reworked how mmu is re-enabled in entry code 
[Jose Abreu]

[1] http://lists.infradead.org/pipermail/linux-snps-arc/2021-August/005326.html

Vineet Gupta (19):
  ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only
  ARC: mm: remove tlb paranoid code
  ARC: mm: move mmu/cache externs out to setup.h
  ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS
  ARC: mm: Enable STRICT_MM_TYPECHECKS
  ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag
  ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)
  ARC: mm: switch pgtable_t back to struct page *
  ARC: mm: switch to asm-generic/pgalloc.h
  ARC: mm: non-functional code cleanup ahead of 3 levels
  ARC: mm: move MMU specific bits out of ASID allocator
  ARC: mm: move MMU specific bits out of entry code ...
  ARC: mm: disintegrate mmu.h (arcv2 bits out)
  ARC: mm: disintegrate pgtable.h into levels and flags
  ARC: mm: hack to allow 2 level build with 4 level code
  ARC: mm: support 3 levels of page tables
  ARC: mm: support 4 levels of page tables
  ARC: mm: vmalloc sync from kernel to user table to update PMD ...
  ARC: mm: introduce _PAGE_TABLE to explicitly link pgd,pud,pmd entries

 arch/arc/Kconfig  |   7 +-
 arch/arc/include/asm/cache.h  |   4 -
 arch/arc/include/asm/entry-compact.h  |   8 -
 arch/arc/include/asm/mmu-arcv2.h  | 103 +++
 arch/arc/include/asm/mmu.h|  73 +
 arch/arc/include/asm/mmu_context.h|  28 +-
 arch/arc/include/asm/page.h   |  74 +++--
 arch/arc/include/asm/pgalloc.h|  81 ++
 arch/arc/include/asm/pgtable-bits-arcv2.h | 151 +++
 arch/arc/include/asm/pgtable-levels.h | 179 
 arch/arc/include/asm/pgtable.h| 315 +-
 arch/arc/include/asm/processor.h  |   2 +-
 arch/arc/include/asm/setup.h  |  12 +-
 arch/arc/kernel/entry-arcv2.S |   1 +
 arch/arc/kernel/entry.S   |   7 +-
 arch/arc/mm/fault.c   |  20 +-
 arch/arc/mm/init.c|   5 +
 arch/arc/mm/ioremap.c |   3 +-
 arch/arc/mm/tlb.c |  68 +
 arch/arc/mm/tlbex.S   |  78 ++
 20 files changed, 591 insertions(+), 628 deletions(-)
 create mode 100644 arch/arc/include/asm/mmu-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-levels.h

-- 
2.25.1


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[PATCH v2 09/19] ARC: mm: switch to asm-generic/pgalloc.h

2021-08-12 Thread Vineet Gupta
With previous patch ARC pgalloc functions are same as generic, hence
switch to that.

Suggested-by: Mike Rapoport 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgalloc.h | 42 +-
 1 file changed, 1 insertion(+), 41 deletions(-)

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 8ab1af3da6e7..0cde9e5eefd7 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -31,6 +31,7 @@
 
 #include 
 #include 
+#include 
 
 static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
@@ -69,47 +70,6 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
return ret;
 }
 
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-   free_page((unsigned long)pgd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
-{
-   pte_t *pte;
-
-   pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_ZERO);
-
-   return pte;
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm)
-{
-   struct page *page;
-
-   page = (pgtable_t)alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_ACCOUNT);
-   if (!page)
-   return NULL;
-
-   if (!pgtable_pte_page_ctor(page)) {
-   __free_page(page);
-   return NULL;
-   }
-
-   return page;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-   free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte_page)
-{
-   pgtable_pte_page_dtor(pte_page);
-   __free_page(pte_page);
-}
-
 #define __pte_free_tlb(tlb, pte, addr)  pte_free((tlb)->mm, pte)
 
 #endif /* _ASM_ARC_PGALLOC_H */
-- 
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[PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

2021-08-12 Thread Vineet Gupta
MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
ARC700 SMP port, it has to be repurposed for reentrant interrupt
handling, while UP port doesn't. We  currently ahandle boe usecases
using a fabricated which has usual issues of dependency nesting and
ugliness.

So clean this up: for ARC700 don't use to cache pgd (even in UP) and do
the opposite for ARCv2.

And while here, switch to canonical pgd_offset().

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/entry-compact.h |  8 
 arch/arc/include/asm/mmu.h   |  4 
 arch/arc/include/asm/mmu_context.h   |  2 +-
 arch/arc/include/asm/pgtable.h   | 23 ---
 arch/arc/mm/fault.c  |  2 +-
 arch/arc/mm/tlb.c|  4 ++--
 arch/arc/mm/tlbex.S  |  2 +-
 7 files changed, 5 insertions(+), 40 deletions(-)

diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 6dbf5cecc8cc..5aab4f93ab8a 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -126,19 +126,11 @@
  * to be saved again on kernel mode stack, as part of pt_regs.
  *-*/
 .macro PROLOG_FREEUP_REG   reg, mem
-#ifndef ARC_USE_SCRATCH_REG
-   sr  \reg, [ARC_REG_SCRATCH_DATA0]
-#else
st  \reg, [\mem]
-#endif
 .endm
 
 .macro PROLOG_RESTORE_REG  reg, mem
-#ifndef ARC_USE_SCRATCH_REG
-   lr  \reg, [ARC_REG_SCRATCH_DATA0]
-#else
ld  \reg, [\mem]
-#endif
 .endm
 
 /*--
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index a81d1975866a..4065335a7922 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -31,10 +31,6 @@
 #define ARC_REG_SCRATCH_DATA0  0x46c
 #endif
 
-#if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
-#defineARC_USE_SCRATCH_REG
-#endif
-
 /* Bits in MMU PID register */
 #define __TLB_ENABLE   (1 << 31)
 #define __PROG_ENABLE  (1 << 30)
diff --git a/arch/arc/include/asm/mmu_context.h 
b/arch/arc/include/asm/mmu_context.h
index df164066e172..49318a126879 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -146,7 +146,7 @@ static inline void switch_mm(struct mm_struct *prev, struct 
mm_struct *next,
 */
cpumask_set_cpu(cpu, mm_cpumask(next));
 
-#ifdef ARC_USE_SCRATCH_REG
+#ifdef CONFIG_ISA_ARCV2
/* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
 #endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 0c3e220bd2b4..80b57c14b430 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -284,29 +284,6 @@ static inline void set_pte_at(struct mm_struct *mm, 
unsigned long addr,
set_pte(ptep, pteval);
 }
 
-/*
- * Macro to quickly access the PGD entry, utlising the fact that some
- * arch may cache the pointer to Page Directory of "current" task
- * in a MMU register
- *
- * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
- * becomes read a register
- *
- * CAUTION***:
- * Kernel code might be dealing with some mm_struct of NON "current"
- * Thus use this macro only when you are certain that "current" is current
- * e.g. when dealing with signal frame setup code etc
- */
-#ifdef ARC_USE_SCRATCH_REG
-#define pgd_offset_fast(mm, addr)  \
-({ \
-   pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0);  \
-   pgd_base + pgd_index(addr); \
-})
-#else
-#define pgd_offset_fast(mm, addr)  pgd_offset(mm, addr)
-#endif
-
 extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
  pte_t *ptep);
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index f5657cb68e4f..41f154320964 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -33,7 +33,7 @@ noinline static int handle_kernel_vaddr_fault(unsigned long 
address)
pud_t *pud, *pud_k;
pmd_t *pmd, *pmd_k;
 
-   pgd = pgd_offset_fast(current->active_mm, address);
+   pgd = pgd_offset(current->active_mm, address);
pgd_k = pgd_offset_k(address);
 
if (!pgd_present(*pgd_k))
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 8696829d37c0..349fb7a75d1d 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -719,8 +719,8 @@ void arc_mmu_init(void)
/* Enable the MMU */
write_aux_reg(ARC_REG_PID, MMU_ENABLE);
 
-   /* In smp we use this reg for interrupt 1 scratch */
-#ifdef ARC_USE_SCRATCH_REG
+   /* In arc700/smp needed for re-entrant interrupt handling */
+#ifdef CONFIG_ISA_ARCV2
/* swapper_pg_dir is the pgd for the kernel,

[PATCH v2 02/19] ARC: mm: remove tlb paranoid code

2021-08-12 Thread Vineet Gupta
This was used back in arc700 days when ASID allocator was fragile.
Not needed in last 5 years

Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig   |  3 ---
 arch/arc/include/asm/mmu.h |  6 -
 arch/arc/mm/tlb.c  | 40 --
 arch/arc/mm/tlbex.S| 50 --
 4 files changed, 99 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 0680b1de0fc3..59d5b2a179f6 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -537,9 +537,6 @@ config ARC_DW2_UNWIND
  If you don't debug the kernel, you can say N, but we may not be able
  to solve problems without frame unwind information
 
-config ARC_DBG_TLB_PARANOIA
-   bool "Paranoia Checks in Low Level TLB Handlers"
-
 config ARC_DBG_JUMP_LABEL
bool "Paranoid checks in Static Keys (jump labels) code"
depends on JUMP_LABEL
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 4065335a7922..38a036508699 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,12 +64,6 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
-#else
-#define tlb_paranoid_check(a, b)
-#endif
-
 void arc_mmu_init(void);
 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
 void read_decode_mmu_bcr(void);
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 349fb7a75d1d..6079dfd129b9 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -400,7 +400,6 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
 *
 * Removing the assumption involves
 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
-* -Fix the TLB paranoid debug code to not trigger false negatives.
 * -More importantly it makes this handler inconsistent with fast-path
 *  TLB Refill handler which always deals with "current"
 *
@@ -423,8 +422,6 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
 
local_irq_save(flags);
 
-   tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr);
-
vaddr &= PAGE_MASK;
 
/* update this PTE credentials */
@@ -818,40 +815,3 @@ void do_tlb_overlap_fault(unsigned long cause, unsigned 
long address,
 
local_irq_restore(flags);
 }
-
-/***
- * Diagnostic Routines
- *  -Called from Low Level TLB Handlers if things don;t look good
- **/
-
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-
-/*
- * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
- * don't match
- */
-void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
-{
-   pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
-  is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
-
-   __asm__ __volatile__("flag 1");
-}
-
-void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
-{
-   unsigned int mmu_asid;
-
-   mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
-
-   /*
-* At the time of a TLB miss/installation
-*   - HW version needs to match SW version
-*   - SW needs to have a valid ASID
-*/
-   if (addr < 0x7000 &&
-   ((mm_asid == MM_CTXT_NO_ASID) ||
- (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK
-   print_asid_mismatch(mm_asid, mmu_asid, 0);
-}
-#endif
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index bcd2909c691f..0b4bb62fa0ab 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -93,11 +93,6 @@ ex_saved_reg1:
st_s  r1, [r0, 4]
st_s  r2, [r0, 8]
st_s  r3, [r0, 12]
-
-   ; VERIFY if the ASID in MMU-PID Reg is same as
-   ; one in Linux data structures
-
-   tlb_paranoid_check_asm
 .endm
 
 .macro TLBMISS_RESTORE_REGS
@@ -146,51 +141,6 @@ ex_saved_reg1:
 
 #endif
 
-;
-;  Troubleshooting Stuff
-;
-
-; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
-; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
-; we use the MMU PID Reg to get current ASID.
-; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
-; So we try to detect this in TLB Mis shandler
-
-.macro tlb_paranoid_check_asm
-
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-
-   GET_CURR_TASK_ON_CPU  r3
-   ld r0, [r3, TASK_ACT_MM]
-   ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
-   breq r0, 0, 55f ; E

[PATCH v2 05/19] ARC: mm: Enable STRICT_MM_TYPECHECKS

2021-08-12 Thread Vineet Gupta
In the past I've refrained from doing this (at least 2 times) due to the
slight code bloat due to ABI implications of pte_t etc becoming struct

Per ARC ABI, functions return struct via memory and not through register
r0, even if the struct would fit in register(s)

 - caller allocates space on stack and passes the address as first arg
   (r0), shifting rest of args by one

 - callee creates return struct in memory (referenced via r0)

This time around the code actually shrunk slightly (due to subtle
inlining heuristic effects), but still slightly inefficient due to
return values passed through memory. That however seems like a small
cost compared to maintenance burden given the impending new mmu support
for page walk etc

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h | 26 --
 arch/arc/mm/ioremap.c   |  2 +-
 2 files changed, 1 insertion(+), 27 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 4a9d33372fe2..c4ac827379cd 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -34,12 +34,6 @@ void copy_user_highpage(struct page *to, struct page *from,
unsigned long u_vaddr, struct vm_area_struct *vma);
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
 
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
@@ -64,26 +58,6 @@ typedef struct {
 
 #define pte_pgprot(x) __pgprot(pte_val(x))
 
-#else /* !STRICT_MM_TYPECHECKS */
-
-#ifdef CONFIG_ARC_HAS_PAE40
-typedef unsigned long long pte_t;
-#else
-typedef unsigned long pte_t;
-#endif
-typedef unsigned long pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x) (x)
-#define pgd_val(x) (x)
-#define pgprot_val(x)  (x)
-#define __pte(x)   (x)
-#define __pgd(x)   (x)
-#define __pgprot(x)(x)
-#define pte_pgprot(x)  (x)
-
-#endif
-
 typedef pte_t * pgtable_t;
 
 /*
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 95c649fbc95a..052bbd8b1e5f 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -39,7 +39,7 @@ void __iomem *ioremap(phys_addr_t paddr, unsigned long size)
if (arc_uncached_addr_space(paddr))
return (void __iomem *)(u32)paddr;
 
-   return ioremap_prot(paddr, size, PAGE_KERNEL_NO_CACHE);
+   return ioremap_prot(paddr, size, pgprot_val(PAGE_KERNEL_NO_CACHE));
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
2.25.1


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Re: [PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

2021-08-12 Thread Vineet Gupta

On 8/11/21 11:18 PM, Mike Rapoport wrote:

On Wed, Aug 11, 2021 at 06:37:19PM -0700, Vineet Gupta wrote:

On 8/11/21 5:31 AM, Mike Rapoport wrote:

+/*
+ * For ARC, pgtable_t is not struct page *, but pte_t * (to avoid
+ * extraneous page_address() calculations) hence can't use
+ * use asm-generic/pgalloc.h which assumes it being struct page *
+ */

Another reason to leave ARC without asm-generic/pgalloc.h was
__get_order_pte() that other arches don't have.
So this and pgtable_t aliased to pte_t * seemed to me too much to bother
then, but probably it's worth reconsidering with addition of 3rd and 4th
levels.

I agree that savings of not havign page_address() might not be huge. However
asm-generic/pgalloc.h only has pte allocation routines and all other
allocation levels come from arch file

asm-generic/pgalloc.h has allocation routines up to PUD.
There is also pgtable_pmd_page_ctor() and pgtable_pmd_page_dtor() called in
the generic versions of PMD allocation, it seems they are not called in ARC
implementation.


:-(


So using asm-generic/pgalloc.h would probably save you some THP debugging ;-)

We may even probably accommodate multi-page PTEs in asm-generic/pgalloc.h
with something like

#ifndef __HAVE_ARCH_PTE_GET_ORDER
static inline int __pte_get_order(void)
{
return 0;
}
#endif


Not needed - those cases are unreal, esoteric at best. I'm working on 
switching back to canonical struct page based pgtable_t, will do that in v2.



Also for ARCv2, given the arbitrary address split and ensuing paging levels
(as well as support for different page sizes) we will need to make sure that
one page is enough to hold any level's paging using say BUILD_BUG_ON. In
fact that should also be done for 3rd and 4th levels for sanity.

Right, these sanity checks would be useful, but they may live in one of .c
files in arch/arc/mm.


Sure !

Thx,
-Vineet

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Re: [PATCH -next] trap: Cleanup trap_init()

2021-08-12 Thread Vineet Gupta

On 8/12/21 5:36 AM, Kefeng Wang wrote:

There are some empty trap_init() in different ARCHs, introduce
a new weak trap_init() function to cleanup them.

Cc: Vineet Gupta
Cc: Russell King
Cc: Yoshinori Sato
Cc: Ley Foon Tan
Cc: Jonas Bonn
Cc: Stefan Kristiansson
Cc: Stafford Horne
Cc: James E.J. Bottomley
Cc: Helge Deller
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Paul Walmsley
Cc: Jeff Dike
Cc: Richard Weinberger
Cc: Anton Ivanov
Cc: Andrew Morton
Signed-off-by: Kefeng Wang
---
  arch/arc/kernel/traps.c  | 5 -


Acked-by: Vineet Gupta   #arch/arc

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Re: [PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

2021-08-11 Thread Vineet Gupta

On 8/11/21 5:31 AM, Mike Rapoport wrote:

+/*
+ * For ARC, pgtable_t is not struct page *, but pte_t * (to avoid
+ * extraneous page_address() calculations) hence can't use
+ * use asm-generic/pgalloc.h which assumes it being struct page *
+ */

Another reason to leave ARC without asm-generic/pgalloc.h was
__get_order_pte() that other arches don't have.
So this and pgtable_t aliased to pte_t * seemed to me too much to bother
then, but probably it's worth reconsidering with addition of 3rd and 4th
levels.


I agree that savings of not havign page_address() might not be huge. 
However asm-generic/pgalloc.h only has pte allocation routines and all 
other allocation levels come from arch file


Also for ARCv2, given the arbitrary address split and ensuing paging 
levels (as well as support for different page sizes) we will need to 
make sure that one page is enough to hold any level's paging using say 
BUILD_BUG_ON. In fact that should also be done for 3rd and 4th levels 
for sanity.


-Vineet



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Re: [PATCH 16/18] ARC: mm: support 4 levels of page tables

2021-08-11 Thread Vineet Gupta

On 8/11/21 5:28 AM, Mike Rapoport wrote:

On Tue, Aug 10, 2021 at 05:42:56PM -0700, Vineet Gupta wrote:

Signed-off-by: Vineet Gupta
---
  arch/arc/include/asm/page.h   | 11 +++
  arch/arc/include/asm/pgalloc.h| 22 +
  arch/arc/include/asm/pgtable-levels.h | 45 ---
  arch/arc/mm/fault.c   |  2 ++
  arch/arc/mm/tlbex.S   |  9 ++
  5 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index df3cc154ae4a..883856f12afe 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
  #define pgd_val(x)((x).pgd)
  #define __pgd(x)  ((pgd_t) { (x) })
  
+#if CONFIG_PGTABLE_LEVELS > 3

+
+typedef struct {
+   unsigned long pud;
+} pud_t;
+
+#define pud_val(x) ((x).pud)
+#define __pud(x)   ((pud_t) { (x) })
+
+#endif
+
  #if CONFIG_PGTABLE_LEVELS > 2
  
  typedef struct {

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 01c2d84418ed..e99c724d9235 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -86,6 +86,28 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
  }
  
  
+#if CONFIG_PGTABLE_LEVELS > 3

+
+static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
+{
+   set_p4d(p4dp, __p4d((unsigned long)pudp));
+}
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+   return (pud_t *)__get_free_page(
+   GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO);
+}
+
+static inline void pud_free(struct mm_struct *mm, pud_t *pudp)
+{
+   free_page((unsigned long)pudp);
+}
+
+#define __pud_free_tlb(tlb, pmd, addr)  pud_free((tlb)->mm, pmd)
+
+#endif
+
  #if CONFIG_PGTABLE_LEVELS > 2
  
  static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)

diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 1c2f022d4ad0..2da3c4e52a91 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -44,8 +44,13 @@
  /*
   * A default 3 level paging testing setup in software walked MMU
   *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ * A default 4 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <3> : <4> : <8> : <13>
   */
  #define PGDIR_SHIFT   28
+#if CONFIG_PGTABLE_LEVELS > 3
+#define PUD_SHIFT  25
+#endif
  #if CONFIG_PGTABLE_LEVELS > 2
  #define PMD_SHIFT 21
  #endif
@@ -56,17 +61,25 @@
  #define PGDIR_MASK(~(PGDIR_SIZE - 1))
  #define PTRS_PER_PGD  BIT(32 - PGDIR_SHIFT)
  
+#if CONFIG_PGTABLE_LEVELS > 3

+#define PUD_SIZE   BIT(PUD_SHIFT)
+#define PUD_MASK   (~(PUD_SIZE - 1))
+#define PTRS_PER_PUD   BIT(PGDIR_SHIFT - PUD_SHIFT)

Maybe move these into the previous #if CONFIG_PGTABLE_LEVELS > 3?


Same reasoning as the prev one. Sure there's a bit more ifdef'ery but I 
think it looks more organized to me. But if you really feel strongly I 
can move the code around.


-Vineet

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Re: [PATCH 15/18] ARC: mm: support 3 levels of page tables

2021-08-11 Thread Vineet Gupta

On 8/11/21 5:24 AM, Mike Rapoport wrote:

On Tue, Aug 10, 2021 at 05:42:55PM -0700, Vineet Gupta wrote:

ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
Forthcoming hw will have multiple levels, so this change preps mm code
for same. It is also fun to try multi levels even on soft-walked code to
ensure generic mm code is robust to handle.

overview


2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on 
pgd
3 levels {pgd, pmd, pte}:
   - pud is folded and pud_* macros point to pgd
   - pmd_* macros operate on actual pmd

code changes


1. #include 

2. Define CONFIG_PGTABLE_LEVELS 3

3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t
3b. Define pmd_val() which actually deals with pmd
 (pmd_offset(), pmd_index() are provided by generic code)
3c. Define pmd_alloc_one() and pmd_free() to allocate pmd
 (pmd_populate/pmd_free already exist)

4. Define pud_none(), pud_bad() macros based on generic pud_val() which
internally pertains to pgd now.
4b. define pud_populate() to just setup pgd

Signed-off-by: Vineet Gupta 
---
  arch/arc/Kconfig  |  4 ++
  arch/arc/include/asm/page.h   | 11 +
  arch/arc/include/asm/pgalloc.h| 22 ++
  arch/arc/include/asm/pgtable-levels.h | 63 ---
  arch/arc/include/asm/processor.h  |  2 +-
  arch/arc/mm/fault.c   |  4 ++
  arch/arc/mm/tlb.c |  4 +-
  arch/arc/mm/tlbex.S   |  9 
  8 files changed, 111 insertions(+), 8 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 59d5b2a179f6..43cb8aaf57a2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -314,6 +314,10 @@ config ARC_HUGEPAGE_16M
  
  endchoice
  
+config PGTABLE_LEVELS

+   int "Number of Page table levels"
+   default 2
+
  config ARC_COMPACT_IRQ_LEVELS
depends on ISA_ARCOMPACT
bool "Setup Timer IRQ as high Priority"
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 313e6f543d2d..df3cc154ae4a 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
  #define pgd_val(x)((x).pgd)
  #define __pgd(x)  ((pgd_t) { (x) })
  
+#if CONFIG_PGTABLE_LEVELS > 2

+
+typedef struct {
+   unsigned long pmd;
+} pmd_t;
+
+#define pmd_val(x) ((x).pmd)
+#define __pmd(x)   ((pmd_t) { (x) })
+
+#endif
+
  typedef struct {
  #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 0cf73431eb89..01c2d84418ed 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -86,6 +86,28 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
  }
  
  
+#if CONFIG_PGTABLE_LEVELS > 2

+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
+{
+   set_pud(pudp, __pud((unsigned long)pmdp));
+}
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+   return (pmd_t *)__get_free_page(
+   GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+   free_page((unsigned long)pmd);
+}
+
+#define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
+
+#endif
+
  /*
   * With software-only page-tables, addr-split for traversal is tweakable and
   * that directly governs how big tables would be at each level.
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 8ece75335bb5..1c2f022d4ad0 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -10,6 +10,8 @@
  #ifndef _ASM_ARC_PGTABLE_LEVELS_H
  #define _ASM_ARC_PGTABLE_LEVELS_H
  
+#if CONFIG_PGTABLE_LEVELS == 2

+
  /*
   * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
   *
@@ -37,16 +39,38 @@
  #define PGDIR_SHIFT   21
  #endif
  
-#define PGDIR_SIZE		BIT(PGDIR_SHIFT)	/* vaddr span, not PDG sz */

-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+#else
+
+/*
+ * A default 3 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ */
+#define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SHIFT  21
+#endif
+
+#endif
  
+#define PGDIR_SIZE		BIT(PGDIR_SHIFT)

+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
  #define PTRS_PER_PGD  BIT(32 - PGDIR_SHIFT)
  
-#define PTRS_PER_PTE		BIT(PGDIR_SHIFT - PAGE_SHIFT)

+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SIZE   BIT(PMD_SHIFT)
+#define PMD_MASK   (~(PMD_SIZE - 1))
+#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)

Maybe move these into the previous #if CONFIG_PGTABLE_LEVELS > 2?


I've kept them separate to distinguish the "configuration" pa

Re: [PATCH 11/18] ARC: mm: move MMU specific bits out of entry code

2021-08-11 Thread Vineet Gupta

On 8/11/21 5:15 AM, Mike Rapoport wrote:

I believe a few words here would be useful even for the future version of
yourself ;-)


"Don't pollute common entry file with MMU versions specific bits (as new 
MMU doesn't have PID register)"


However Jose thankfully pointed me (off list) that this patch is broken 
(based on some internal emails).
Any Machine check disables MMU but we now we only re-enable for TLB 
faults related MC, so this will have to be redone.


Thx,
-Vineet

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Re: [PATCH 06/18] ARC: mm: Enable STRICT_MM_TYPECHECKS

2021-08-11 Thread Vineet Gupta

On 8/11/21 5:04 AM, Mike Rapoport wrote:

On Tue, Aug 10, 2021 at 05:42:46PM -0700, Vineet Gupta wrote:

In the past I've refrained from doing this (atleast 2 times) due to the

 ^ at least


slight code bloat due to ABI implications of pte_t etc becoming sttuct

  ^ struct

Per ARC ABI, functions return struct via memory and not through register
r0, even if the struct would fits in register(s)

   ^ fit


Fixed.


  - caller allocates space on stack and passes the address as first arg
(r0), shifting rest of args by one

  - callee creates return struct in memory (referenced via r0)

This time around the code actually shrunk slightly (due to subtle
inlining heuristic effects), but still slightly inefficient due to
return values passed through memory. That however seems like a small

Out of curiosity, is this actually measurable on real world applications?


Not really, but they look hideous to an objdump hunkie like me (who 
treats waste of electrons like wasting food) and wondering what piece of 
art your compiler is spitting out ;-) only to realize that is source 
code induced.


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Re: [PATCH 07/18] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

2021-08-11 Thread Vineet Gupta

On 8/10/21 10:18 PM, Mike Rapoport wrote:

-   return ioremap_prot(paddr, size, pgprot_val(PAGE_KERNEL_NO_CACHE));
+   return ioremap_prot(paddr, size,
+   pgprot_val(pgprot_noncached(PAGE_KERNEL)));

But this becomes _PAGE_CACHEABLE now. What did I miss?


We now use pgprot_noncached()

arch/arc/include/asm/pgtable.h:30:#define pgprot_noncached(prot)    
(__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))


-Vineet

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Re: [PATCH 04/18] ARC: mm: remove pgd_offset_fast

2021-08-11 Thread Vineet Gupta

On 8/10/21 10:12 PM, Mike Rapoport wrote:

On Tue, Aug 10, 2021 at 05:42:44PM -0700, Vineet Gupta wrote:

Signed-off-by: Vineet Gupta 
---
  arch/arc/include/asm/pgtable.h | 23 ---
  arch/arc/mm/fault.c|  2 +-
  2 files changed, 1 insertion(+), 24 deletions(-)

Shouldn't this be a part of the patch that removed usage of the scratch reg
for pgd?


Yep, now folded in there. Also updated prev patch's terse commit log.

Thx,
-Vineet

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Re: [PATCH 03/18] ARC: mm: move mmu/cache externs out to setup.h

2021-08-11 Thread Vineet Gupta

Hi Mike,

On 8/10/21 10:10 PM, Mike Rapoport wrote:

Hi Vineet,

On Tue, Aug 10, 2021 at 05:42:43PM -0700, Vineet Gupta wrote:

Signed-off-by: Vineet Gupta 

Hmm, this one seems odd. Try https://www.kernel.com/ ;-)


Oops, last minute switch to my kernel.org address - this update was not 
atomic ;-)



Signed-off-by: Vineet Gupta 
---
  arch/arc/include/asm/cache.h |  4 
  arch/arc/include/asm/mmu.h   |  4 
  arch/arc/include/asm/setup.h | 12 ++--

A sentence about why these move would have been nice.


Sure
>
"Don't pollute mmu.h and cache.h with some of ARC internal bootlog/setup 
related functions.

move them aside to setup.h"

Thx for taking the time to review !

-Vineet

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[PATCH 18/18] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd, pud, pmd entries

2021-08-10 Thread Vineet Gupta
ARCv3 hardware walker expects Table Descriptors to have b'11 in LSB bits
to continue moving to next level.

This commits adds that (to ARCv2 code) and ensures that it works in
software walked regime.

The pte entries stil need tagging, but that is not possible in ARCv2
since the LSB 2 bits are currently used.

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgalloc.h| 6 +++---
 arch/arc/include/asm/pgtable-bits-arcv2.h | 2 ++
 arch/arc/include/asm/pgtable-levels.h | 6 +++---
 arch/arc/mm/tlbex.S   | 4 +++-
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index e99c724d9235..230d43a998af 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -47,7 +47,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t 
*ptep)
 *
 * The cast itself is needed given simplistic definition of set_pmd()
 */
-   set_pmd(pmdp, __pmd((unsigned long)ptep));
+   set_pmd(pmdp, __pmd((unsigned long)ptep | _PAGE_TABLE));
 }
 
 /*
@@ -90,7 +90,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 
 static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
 {
-   set_p4d(p4dp, __p4d((unsigned long)pudp));
+   set_p4d(p4dp, __p4d((unsigned long)pudp | _PAGE_TABLE));
 }
 
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
@@ -112,7 +112,7 @@ static inline void pud_free(struct mm_struct *mm, pud_t 
*pudp)
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
 {
-   set_pud(pudp, __pud((unsigned long)pmdp));
+   set_pud(pudp, __pud((unsigned long)pmdp | _PAGE_TABLE));
 }
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h 
b/arch/arc/include/asm/pgtable-bits-arcv2.h
index 183d23bc1e00..54aba0d3ae34 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -32,6 +32,8 @@
 #define _PAGE_HW_SZ0
 #endif
 
+#define _PAGE_TABLE0x3
+
 /* Defaults for every user page */
 #define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
 
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 2da3c4e52a91..6c7a8360d986 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -98,7 +98,7 @@
 
 /* In 4 level paging, p4d_* macros work on pgd */
 #define p4d_none(x)(!p4d_val(x))
-#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
+#define p4d_bad(x) (!(p4d_val(x) & _PAGE_TABLE))
 #define p4d_present(x) (p4d_val(x))
 #define p4d_clear(xp)  do { p4d_val(*(xp)) = 0; } while (0)
 #define p4d_pgtable(p4d)   ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
@@ -120,7 +120,7 @@
  * In 4 level paging, pud_* macros work on pud
  */
 #define pud_none(x)(!pud_val(x))
-#define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
+#define pud_bad(x) (!(pud_val(x) & _PAGE_TABLE))
 #define pud_present(x) (pud_val(x))
 #define pud_clear(xp)  do { pud_val(*(xp)) = 0; } while (0)
 #define pud_pgtable(pud)   ((pmd_t *)(pud_val(pud) & PAGE_MASK))
@@ -147,7 +147,7 @@
  * In 3+ level paging (pgd -> pmd -> pte), pmd_* macros work on pmd
  */
 #define pmd_none(x)(!pmd_val(x))
-#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
+#define pmd_bad(pmd)   (!(pmd_val(pmd) & _PAGE_TABLE))
 #define pmd_present(x) (pmd_val(x))
 #define pmd_clear(xp)  do { pmd_val(*(xp)) = 0; } while (0)
 #define pmd_page_vaddr(pmd)(pmd_val(pmd) & PAGE_MASK)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index e1831b6fafa9..24a9670186b3 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -171,11 +171,12 @@ ex_saved_reg1:
lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
ld.as   r3, [r1, r0]; PGD entry corresp to faulting addr
tst r3, r3
-   bz  do_slow_path_pf ; if no Page Table, do page fault
+   bz  do_slow_path_pf ; next level table missing, handover to 
linux vm code
 
 #if CONFIG_PGTABLE_LEVELS > 3
lsr r0, r2, PUD_SHIFT   ; Bits for indexing into PUD
and r0, r0, (PTRS_PER_PUD - 1)
+   bmskn   r3, r3, 1   ; clear _PAGE_TABLE bits
ld.as   r1, [r3, r0]; PMD entry
tst r1, r1
bz  do_slow_path_pf
@@ -185,6 +186,7 @@ ex_saved_reg1:
 #if CONFIG_PGTABLE_LEVELS > 2
lsr r0, r2, PMD_SHIFT   ; Bits for indexing into PMD
and r0, r0, (PTRS_PER_PMD - 1)
+   bmskn   r3, r3, 1   ; clear _PAGE_TABLE bits
ld.as   r1, [r3, r0]; PMD entry
tst r

[PATCH 15/18] ARC: mm: support 3 levels of page tables

2021-08-10 Thread Vineet Gupta
ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
Forthcoming hw will have multiple levels, so this change preps mm code
for same. It is also fun to try multi levels even on soft-walked code to
ensure generic mm code is robust to handle.

overview


2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on 
pgd
3 levels {pgd, pmd, pte}:
  - pud is folded and pud_* macros point to pgd
  - pmd_* macros operate on actual pmd

code changes


1. #include 

2. Define CONFIG_PGTABLE_LEVELS 3

3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t
3b. Define pmd_val() which actually deals with pmd
(pmd_offset(), pmd_index() are provided by generic code)
3c. Define pmd_alloc_one() and pmd_free() to allocate pmd
(pmd_populate/pmd_free already exist)

4. Define pud_none(), pud_bad() macros based on generic pud_val() which
   internally pertains to pgd now.
4b. define pud_populate() to just setup pgd

Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig  |  4 ++
 arch/arc/include/asm/page.h   | 11 +
 arch/arc/include/asm/pgalloc.h| 22 ++
 arch/arc/include/asm/pgtable-levels.h | 63 ---
 arch/arc/include/asm/processor.h  |  2 +-
 arch/arc/mm/fault.c   |  4 ++
 arch/arc/mm/tlb.c |  4 +-
 arch/arc/mm/tlbex.S   |  9 
 8 files changed, 111 insertions(+), 8 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 59d5b2a179f6..43cb8aaf57a2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -314,6 +314,10 @@ config ARC_HUGEPAGE_16M
 
 endchoice
 
+config PGTABLE_LEVELS
+   int "Number of Page table levels"
+   default 2
+
 config ARC_COMPACT_IRQ_LEVELS
depends on ISA_ARCOMPACT
bool "Setup Timer IRQ as high Priority"
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 313e6f543d2d..df3cc154ae4a 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
 #define pgd_val(x) ((x).pgd)
 #define __pgd(x)   ((pgd_t) { (x) })
 
+#if CONFIG_PGTABLE_LEVELS > 2
+
+typedef struct {
+   unsigned long pmd;
+} pmd_t;
+
+#define pmd_val(x) ((x).pmd)
+#define __pmd(x)   ((pmd_t) { (x) })
+
+#endif
+
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 0cf73431eb89..01c2d84418ed 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -86,6 +86,28 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 }
 
 
+#if CONFIG_PGTABLE_LEVELS > 2
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
+{
+   set_pud(pudp, __pud((unsigned long)pmdp));
+}
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+   return (pmd_t *)__get_free_page(
+   GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+   free_page((unsigned long)pmd);
+}
+
+#define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
+
+#endif
+
 /*
  * With software-only page-tables, addr-split for traversal is tweakable and
  * that directly governs how big tables would be at each level.
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 8ece75335bb5..1c2f022d4ad0 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -10,6 +10,8 @@
 #ifndef _ASM_ARC_PGTABLE_LEVELS_H
 #define _ASM_ARC_PGTABLE_LEVELS_H
 
+#if CONFIG_PGTABLE_LEVELS == 2
+
 /*
  * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
  *
@@ -37,16 +39,38 @@
 #define PGDIR_SHIFT21
 #endif
 
-#define PGDIR_SIZE BIT(PGDIR_SHIFT)/* vaddr span, not PDG 
sz */
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+#else
+
+/*
+ * A default 3 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ */
+#define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SHIFT  21
+#endif
+
+#endif
 
+#define PGDIR_SIZE BIT(PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
 #define PTRS_PER_PGD   BIT(32 - PGDIR_SHIFT)
 
-#define PTRS_PER_PTE   BIT(PGDIR_SHIFT - PAGE_SHIFT)
+#if CONFIG_PGTABLE_LEVELS > 2
+#define PMD_SIZE   BIT(PMD_SHIFT)
+#define PMD_MASK   (~(PMD_SIZE - 1))
+#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)
+#endif
+
+#define PTRS_PER_PTE   BIT(PMD_SHIFT - PAGE_SHIFT)
 
 #ifndef __ASSEMBLY__
 
+#if CONFIG_PGTABLE_LEVELS > 2
+#include 
+#else
 #include 
+#endif
 
 /*
  * 1st level paging: pgd
@@ -57,9 +81,35 @@
 #define pgd_ERROR(e) \
pr

[PATCH 17/18] ARC: mm: vmalloc sync from kernel to user table to update PMD ...

2021-08-10 Thread Vineet Gupta
... not PGD

vmalloc() sets up the kernel page table (starting from @swapper_pg_dir).
But when vmalloc area is accessed in context of a user task, say opening
terminal in n_tty_open(), the user page tables need to be synced from
kernel page tables so that TLB entry is created in "user context".

The old code was doing this incorrectly, as it was updating the user pgd
entry (first level itself) to point to kernel pud table (2nd level),
effectively yanking away the entire user space translation with kernel one.

The correct way to do this is to ONLY update a user space pgd/pud/pmd entry
if it is not popluated already. This ensures that only the missing leaf
pmd entry gets updated to point to relevant kernel pte table.

>From code change pov, we are chaging the pattern:

p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
if (!p4d_present(*p4d_k))
goto bad_area;
set_p4d(p4d, *p4d_k);

with
p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
if (p4d_none(*p4d_k))
goto bad_area;
if (!p4d_present(*p4d))
set_p4d(p4d, *p4d_k);

Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/fault.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index f8994164fa36..5787c261c9a4 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -36,31 +36,31 @@ noinline static int handle_kernel_vaddr_fault(unsigned long 
address)
pgd = pgd_offset(current->active_mm, address);
pgd_k = pgd_offset_k(address);
 
-   if (!pgd_present(*pgd_k))
+   if (pgd_none (*pgd_k))
goto bad_area;
-
-   set_pgd(pgd, *pgd_k);
+   if (!pgd_present(*pgd))
+   set_pgd(pgd, *pgd_k);
 
p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
-   if (!p4d_present(*p4d_k))
+   if (p4d_none(*p4d_k))
goto bad_area;
-
-   set_p4d(p4d, *p4d_k);
+   if (!p4d_present(*p4d))
+   set_p4d(p4d, *p4d_k);
 
pud = pud_offset(p4d, address);
pud_k = pud_offset(p4d_k, address);
-   if (!pud_present(*pud_k))
+   if (pud_none(*pud_k))
goto bad_area;
-
-   set_pud(pud, *pud_k);
+   if (!pud_present(*pud))
+   set_pud(pud, *pud_k);
 
pmd = pmd_offset(pud, address);
pmd_k = pmd_offset(pud_k, address);
-   if (!pmd_present(*pmd_k))
+   if (pmd_none(*pmd_k))
goto bad_area;
-
-   set_pmd(pmd, *pmd_k);
+   if (!pmd_present(*pmd))
+   set_pmd(pmd, *pmd_k);
 
/* XXX: create the TLB entry here */
return 0;
-- 
2.25.1


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[PATCH 14/18] ARC: mm: hack to allow 2 level build with 4 level code

2021-08-10 Thread Vineet Gupta
PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-*
but only for !__ASSEMBLY__

tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs
for CONFIG_PGTABLE_LEVEL={2,3} and works for 4.

So add a workaround local to tlbex.S - the proper fix is to change
asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too

Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/tlbex.S | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 6b5872197005..d08bd09a0afc 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -145,6 +145,14 @@ ex_saved_reg1:
 ;TLB Miss handling Code
 ;
 
+#ifndef PMD_SHIFT
+#define PMD_SHIFT PUD_SHIFT
+#endif
+
+#ifndef PUD_SHIFT
+#define PUD_SHIFT PGDIR_SHIFT
+#endif
+
 ;-
 ; This macro does the page-table lookup for the faulting address.
 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
-- 
2.25.1


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[PATCH 11/18] ARC: mm: move MMU specific bits out of entry code

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/kernel/entry.S | 6 --
 arch/arc/mm/tlb.c   | 3 +++
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 2cb8dfe866b6..684efd094520 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -101,12 +101,6 @@ ENTRY(EV_MachineCheck)
lr  r0, [efa]
mov r1, sp
 
-   ; hardware auto-disables MMU, re-enable it to allow kernel vaddr
-   ; access for say stack unwinding of modules for crash dumps
-   lr  r3, [ARC_REG_PID]
-   or  r3, r3, MMU_ENABLE
-   sr  r3, [ARC_REG_PID]
-
lsr r3, r2, 8
bmskr3, r3, 7
brner3, ECR_C_MCHK_DUP_TLB, 1f
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index b68d5798327b..34f16e0b41e6 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -813,5 +813,8 @@ void do_tlb_overlap_fault(unsigned long cause, unsigned 
long address,
}
}
 
+   /* Re-enable MMU as hardware may have auto-disabled it upon exception */
+   write_aux_reg(ARC_REG_PID, read_aux_reg(ARC_REG_PID) | MMU_ENABLE);
+
local_irq_restore(flags);
 }
-- 
2.25.1


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[PATCH 16/18] ARC: mm: support 4 levels of page tables

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h   | 11 +++
 arch/arc/include/asm/pgalloc.h| 22 +
 arch/arc/include/asm/pgtable-levels.h | 45 ---
 arch/arc/mm/fault.c   |  2 ++
 arch/arc/mm/tlbex.S   |  9 ++
 5 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index df3cc154ae4a..883856f12afe 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -41,6 +41,17 @@ typedef struct {
 #define pgd_val(x) ((x).pgd)
 #define __pgd(x)   ((pgd_t) { (x) })
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+typedef struct {
+   unsigned long pud;
+} pud_t;
+
+#define pud_val(x) ((x).pud)
+#define __pud(x)   ((pud_t) { (x) })
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
 typedef struct {
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 01c2d84418ed..e99c724d9235 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -86,6 +86,28 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 }
 
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
+{
+   set_p4d(p4dp, __p4d((unsigned long)pudp));
+}
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+   return (pud_t *)__get_free_page(
+   GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO);
+}
+
+static inline void pud_free(struct mm_struct *mm, pud_t *pudp)
+{
+   free_page((unsigned long)pudp);
+}
+
+#define __pud_free_tlb(tlb, pmd, addr)  pud_free((tlb)->mm, pmd)
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
diff --git a/arch/arc/include/asm/pgtable-levels.h 
b/arch/arc/include/asm/pgtable-levels.h
index 1c2f022d4ad0..2da3c4e52a91 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -44,8 +44,13 @@
 /*
  * A default 3 level paging testing setup in software walked MMU
  *   MMUv4 (8K page): <4> : <7> : <8> : <13>
+ * A default 4 level paging testing setup in software walked MMU
+ *   MMUv4 (8K page): <4> : <3> : <4> : <8> : <13>
  */
 #define PGDIR_SHIFT28
+#if CONFIG_PGTABLE_LEVELS > 3
+#define PUD_SHIFT  25
+#endif
 #if CONFIG_PGTABLE_LEVELS > 2
 #define PMD_SHIFT  21
 #endif
@@ -56,17 +61,25 @@
 #define PGDIR_MASK (~(PGDIR_SIZE - 1))
 #define PTRS_PER_PGD   BIT(32 - PGDIR_SHIFT)
 
+#if CONFIG_PGTABLE_LEVELS > 3
+#define PUD_SIZE   BIT(PUD_SHIFT)
+#define PUD_MASK   (~(PUD_SIZE - 1))
+#define PTRS_PER_PUD   BIT(PGDIR_SHIFT - PUD_SHIFT)
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 #define PMD_SIZE   BIT(PMD_SHIFT)
 #define PMD_MASK   (~(PMD_SIZE - 1))
-#define PTRS_PER_PMD   BIT(PGDIR_SHIFT - PMD_SHIFT)
+#define PTRS_PER_PMD   BIT(PUD_SHIFT - PMD_SHIFT)
 #endif
 
 #define PTRS_PER_PTE   BIT(PMD_SHIFT - PAGE_SHIFT)
 
 #ifndef __ASSEMBLY__
 
-#if CONFIG_PGTABLE_LEVELS > 2
+#if CONFIG_PGTABLE_LEVELS > 3
+#include 
+#elif CONFIG_PGTABLE_LEVELS > 2
 #include 
 #else
 #include 
@@ -81,9 +94,31 @@
 #define pgd_ERROR(e) \
pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
+#if CONFIG_PGTABLE_LEVELS > 3
+
+/* In 4 level paging, p4d_* macros work on pgd */
+#define p4d_none(x)(!p4d_val(x))
+#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
+#define p4d_present(x) (p4d_val(x))
+#define p4d_clear(xp)  do { p4d_val(*(xp)) = 0; } while (0)
+#define p4d_pgtable(p4d)   ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
+#define p4d_page(p4d)  virt_to_page(p4d_pgtable(p4d))
+#define set_p4d(p4dp, p4d) (*(p4dp) = p4d)
+
+/*
+ * 2nd level paging: pud
+ */
+#define pud_ERROR(e) \
+   pr_crit("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
+
+#endif
+
 #if CONFIG_PGTABLE_LEVELS > 2
 
-/* In 3 level paging, pud_* macros work on pgd */
+/*
+ * In 3 level paging, pud_* macros work on pgd
+ * In 4 level paging, pud_* macros work on pud
+ */
 #define pud_none(x)(!pud_val(x))
 #define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
 #define pud_present(x) (pud_val(x))
@@ -93,7 +128,7 @@
 #define set_pud(pudp, pud) (*(pudp) = pud)
 
 /*
- * 2nd level paging: pmd
+ * 3rd level paging: pmd
  */
 #define pmd_ERROR(e) \
pr_crit("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
@@ -121,7 +156,7 @@
 #define pmd_pgtable(pmd)   ((pgtable_t) pmd_page_vaddr(pmd))
 
 /*
- * 3rd level paging: pte
+ * 4th level paging: pte
  */
 #define pte_ERROR(e) \
pr_crit("%s:%d: bad pte %08lx.\n&

[PATCH 03/18] ARC: mm: move mmu/cache externs out to setup.h

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/cache.h |  4 
 arch/arc/include/asm/mmu.h   |  4 
 arch/arc/include/asm/setup.h | 12 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d8ece4292388..f0f1fc5d62b6 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -62,10 +62,6 @@
 #define ARCH_SLAB_MINALIGN 8
 #endif
 
-extern void arc_cache_init(void);
-extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
-extern void read_decode_cache_bcr(void);
-
 extern int ioc_enable;
 extern unsigned long perip_base, perip_end;
 
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 38a036508699..762cfe66e16b 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,10 +64,6 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
-void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-void read_decode_mmu_bcr(void);
-
 static inline int is_pae40_enabled(void)
 {
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h
index 01f85478170d..028a8cf76206 100644
--- a/arch/arc/include/asm/setup.h
+++ b/arch/arc/include/asm/setup.h
@@ -2,8 +2,8 @@
 /*
  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  */
-#ifndef __ASMARC_SETUP_H
-#define __ASMARC_SETUP_H
+#ifndef __ASM_ARC_SETUP_H
+#define __ASM_ARC_SETUP_H
 
 
 #include 
@@ -34,4 +34,12 @@ long __init arc_get_mem_sz(void);
 #define IS_AVAIL2(v, s, cfg)   IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg))
 #define IS_AVAIL3(v, v2, s)IS_AVAIL1(v, s), IS_AVAIL1(v, 
IS_DISABLED_RUN(v2))
 
+extern void arc_mmu_init(void);
+extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
+extern void read_decode_mmu_bcr(void);
+
+extern void arc_cache_init(void);
+extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
+extern void read_decode_cache_bcr(void);
+
 #endif /* __ASMARC_SETUP_H */
-- 
2.25.1


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[PATCH 13/18] ARC: mm: disintegrate pgtable.h into levels and flags

2021-08-10 Thread Vineet Gupta
 - pgtable-bits-arcv2.h (MMU specific page table flags)
 - pgtable-levels.h (paging levels)

No functional changes, but paves way for easy addition of new MMU code
with different bits and levels etc

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgtable-bits-arcv2.h | 149 
 arch/arc/include/asm/pgtable-levels.h |  91 +++
 arch/arc/include/asm/pgtable.h| 277 +-
 3 files changed, 244 insertions(+), 273 deletions(-)
 create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-levels.h

diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h 
b/arch/arc/include/asm/pgtable-bits-arcv2.h
new file mode 100644
index ..183d23bc1e00
--- /dev/null
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
+ */
+
+/*
+ * page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
+ * There correspond to the corresponding bits in the TLB
+ */
+
+#ifndef _ASM_ARC_PGTABLE_BITS_ARCV2_H
+#define _ASM_ARC_PGTABLE_BITS_ARCV2_H
+
+#ifdef CONFIG_ARC_CACHE_PAGES
+#define _PAGE_CACHEABLE(1 << 0)  /* Cached (H) */
+#else
+#define _PAGE_CACHEABLE0
+#endif
+
+#define _PAGE_EXECUTE  (1 << 1)  /* User Execute  (H) */
+#define _PAGE_WRITE(1 << 2)  /* User Write(H) */
+#define _PAGE_READ (1 << 3)  /* User Read (H) */
+#define _PAGE_ACCESSED (1 << 4)  /* Accessed  (s) */
+#define _PAGE_DIRTY(1 << 5)  /* Modified  (s) */
+#define _PAGE_SPECIAL  (1 << 6)
+#define _PAGE_GLOBAL   (1 << 8)  /* ASID agnostic (H) */
+#define _PAGE_PRESENT  (1 << 9)  /* PTE/TLB Valid (H) */
+
+#ifdef CONFIG_ARC_MMU_V4
+#define _PAGE_HW_SZ(1 << 10)  /* Normal/super (H) */
+#else
+#define _PAGE_HW_SZ0
+#endif
+
+/* Defaults for every user page */
+#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
+
+/* Set of bits not changed in pte_modify */
+#define _PAGE_CHG_MASK (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
+  _PAGE_SPECIAL)
+
+/* More Abbrevaited helpers */
+#define PAGE_U_NONE __pgprot(___DEF)
+#define PAGE_U_R__pgprot(___DEF | _PAGE_READ)
+#define PAGE_U_W_R  __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
+#define PAGE_U_X_R  __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
+#define PAGE_U_X_W_R__pgprot(___DEF \
+   | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
+#define PAGE_KERNEL __pgprot(___DEF | _PAGE_GLOBAL \
+   | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
+
+#define PAGE_SHAREDPAGE_U_W_R
+
+#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
+
+/*
+ * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
+ *
+ * Certain cases have 1:1 mapping
+ *  e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
+ *   which directly corresponds to  PAGE_U_X_R
+ *
+ * Other rules which cause the divergence from 1:1 mapping
+ *
+ *  1. Although ARC700 can do exclusive execute/write protection (meaning R
+ * can be tracked independet of X/W unlike some other CPUs), still to
+ * keep things consistent with other archs:
+ *  -Write implies Read:   W => R
+ *  -Execute implies Read: X => R
+ *
+ *  2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
+ * This is to enable COW mechanism
+ */
+   /* xwr */
+#define __P000  PAGE_U_NONE
+#define __P001  PAGE_U_R
+#define __P010  PAGE_U_R   /* Pvt-W => !W */
+#define __P011  PAGE_U_R   /* Pvt-W => !W */
+#define __P100  PAGE_U_X_R /* X => R */
+#define __P101  PAGE_U_X_R
+#define __P110  PAGE_U_X_R /* Pvt-W => !W and X => R */
+#define __P111  PAGE_U_X_R /* Pvt-W => !W */
+
+#define __S000  PAGE_U_NONE
+#define __S001  PAGE_U_R
+#define __S010  PAGE_U_W_R /* W => R */
+#define __S011  PAGE_U_W_R
+#define __S100  PAGE_U_X_R /* X => R */
+#define __S101  PAGE_U_X_R
+#define __S110  PAGE_U_X_W_R   /* X => R */
+#define __S111  PAGE_U_X_W_R
+
+#ifndef __ASSEMBLY__
+
+#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
+#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
+#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
+#define pte_special(pte)   (pte_val(pte) & _PAGE_SPECIAL)
+
+#define PTE_BIT_FUNC(fn, op) \
+   static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+PTE_BIT_FUNC(mknotpresent, &= ~(_PAGE_PRESENT));
+PTE_BIT_FUNC(wrprotect,&= ~(_PAGE_WRITE));
+PTE_BIT_FUNC(mkwrite,  |= (_PAGE_WRITE));
+PTE_BIT_FUNC(mkclean,  &= ~(_PAGE_DIRTY));
+PTE_BIT_FUNC(mkdirty,  |= (_PA

[PATCH 06/18] ARC: mm: Enable STRICT_MM_TYPECHECKS

2021-08-10 Thread Vineet Gupta
In the past I've refrained from doing this (atleast 2 times) due to the
slight code bloat due to ABI implications of pte_t etc becoming sttuct

Per ARC ABI, functions return struct via memory and not through register
r0, even if the struct would fits in register(s)

 - caller allocates space on stack and passes the address as first arg
   (r0), shifting rest of args by one

 - callee creates return struct in memory (referenced via r0)

This time around the code actually shrunk slightly (due to subtle
inlining heuristic effects), but still slightly inefficient due to
return values passed through memory. That however seems like a small
cost compared to maintenance burden given the impending new mmu support
for page walk etc

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h | 26 --
 arch/arc/mm/ioremap.c   |  2 +-
 2 files changed, 1 insertion(+), 27 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 4a9d33372fe2..c4ac827379cd 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -34,12 +34,6 @@ void copy_user_highpage(struct page *to, struct page *from,
unsigned long u_vaddr, struct vm_area_struct *vma);
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
 
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
@@ -64,26 +58,6 @@ typedef struct {
 
 #define pte_pgprot(x) __pgprot(pte_val(x))
 
-#else /* !STRICT_MM_TYPECHECKS */
-
-#ifdef CONFIG_ARC_HAS_PAE40
-typedef unsigned long long pte_t;
-#else
-typedef unsigned long pte_t;
-#endif
-typedef unsigned long pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x) (x)
-#define pgd_val(x) (x)
-#define pgprot_val(x)  (x)
-#define __pte(x)   (x)
-#define __pgd(x)   (x)
-#define __pgprot(x)(x)
-#define pte_pgprot(x)  (x)
-
-#endif
-
 typedef pte_t * pgtable_t;
 
 /*
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 95c649fbc95a..052bbd8b1e5f 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -39,7 +39,7 @@ void __iomem *ioremap(phys_addr_t paddr, unsigned long size)
if (arc_uncached_addr_space(paddr))
return (void __iomem *)(u32)paddr;
 
-   return ioremap_prot(paddr, size, PAGE_KERNEL_NO_CACHE);
+   return ioremap_prot(paddr, size, pgprot_val(PAGE_KERNEL_NO_CACHE));
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
2.25.1


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[PATCH 10/18] ARC: mm: move MMU specific bits out of ASID allocator

2021-08-10 Thread Vineet Gupta
And while at it, rewrite commentary on ASID allocator

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/mmu.h | 13 +
 arch/arc/include/asm/mmu_context.h | 28 +---
 arch/arc/mm/tlb.c  | 11 ---
 3 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 762cfe66e16b..2cabdfaf2afb 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,6 +64,19 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
+static void inline mmu_setup_asid(struct mm_struct *mm, unsigned int asid)
+{
+   write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
+}
+
+static void inline mmu_setup_pgd(struct mm_struct *mm, pgd_t *pgd)
+{
+   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
+#ifdef CONFIG_ISA_ARCV2
+   write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
+#endif
+}
+
 static inline int is_pae40_enabled(void)
 {
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
diff --git a/arch/arc/include/asm/mmu_context.h 
b/arch/arc/include/asm/mmu_context.h
index 49318a126879..dda471f5f05b 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -15,22 +15,23 @@
 #ifndef _ASM_ARC_MMU_CONTEXT_H
 #define _ASM_ARC_MMU_CONTEXT_H
 
-#include 
-#include 
 #include 
 
+#include 
 #include 
 
-/* ARC700 ASID Management
+/* ARC ASID Management
+ *
+ * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
+ * context-switch.
  *
- * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
- * with same vaddr (different tasks) to co-exit. This provides for
- * "Fast Context Switch" i.e. no TLB flush on ctxt-switch
+ * ASID is managed per cpu, so task threads across CPUs can have different
+ * ASID. Global ASID management is needed if hardware supports TLB shootdown
+ * and/or shared TLB across cores, which ARC doesn't.
  *
- * Linux assigns each task a unique ASID. A simple round-robin allocation
- * of H/w ASID is done using software tracker @asid_cpu.
- * When it reaches max 255, the allocation cycle starts afresh by flushing
- * the entire TLB and wrapping ASID back to zero.
+ * Each task is assigned unique ASID, with a simple round-robin allocator
+ * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started
+ * over from 0, and TLB is flushed
  *
  * A new allocation cycle, post rollover, could potentially reassign an ASID
  * to a different task. Thus the rule is to refresh the ASID in a new cycle.
@@ -93,7 +94,7 @@ static inline void get_new_mmu_context(struct mm_struct *mm)
asid_mm(mm, cpu) = asid_cpu(cpu);
 
 set_hw:
-   write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE);
+   mmu_setup_asid(mm, hw_pid(mm, cpu));
 
local_irq_restore(flags);
 }
@@ -146,10 +147,7 @@ static inline void switch_mm(struct mm_struct *prev, 
struct mm_struct *next,
 */
cpumask_set_cpu(cpu, mm_cpumask(next));
 
-#ifdef CONFIG_ISA_ARCV2
-   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
-   write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
-#endif
+   mmu_setup_pgd(next, next->pgd);
 
get_new_mmu_context(next);
 }
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 15cbc285b0de..b68d5798327b 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -716,14 +716,11 @@ void arc_mmu_init(void)
if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
panic("Hardware doesn't support PAE40\n");
 
-   /* Enable the MMU */
-   write_aux_reg(ARC_REG_PID, MMU_ENABLE);
+   /* Enable the MMU with ASID 0 */
+   mmu_setup_asid(NULL, 0);
 
-   /* In arc700/smp needed for re-entrant interrupt handling */
-#ifdef CONFIG_ISA_ARCV2
-   /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
-   write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
-#endif
+   /* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */
+   mmu_setup_pgd(NULL, swapper_pg_dir);
 
if (pae40_exist_but_not_enab())
write_aux_reg(ARC_REG_TLBPD1HI, 0);
-- 
2.25.1


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[PATCH 07/18] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

2021-08-10 Thread Vineet Gupta
and remove the one off uncached definition for ARC

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgtable.h | 3 ---
 arch/arc/mm/ioremap.c  | 3 ++-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 80b57c14b430..b054c14f8bf6 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -103,9 +103,6 @@
  */
 #define PAGE_KERNEL  __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE)
 
-/* ioremap */
-#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
-
 /* Masks for actual TLB "PD"s */
 #define PTE_BITS_IN_PD0(_PAGE_GLOBAL | _PAGE_PRESENT | 
_PAGE_HW_SZ)
 #define PTE_BITS_RWX   (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 052bbd8b1e5f..0ee75aca6e10 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -39,7 +39,8 @@ void __iomem *ioremap(phys_addr_t paddr, unsigned long size)
if (arc_uncached_addr_space(paddr))
return (void __iomem *)(u32)paddr;
 
-   return ioremap_prot(paddr, size, pgprot_val(PAGE_KERNEL_NO_CACHE));
+   return ioremap_prot(paddr, size,
+   pgprot_val(pgprot_noncached(PAGE_KERNEL)));
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
2.25.1


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[PATCH 12/18] ARC: mm: disintegrate mmu.h (arcv2 bits out)

2021-08-10 Thread Vineet Gupta
non functional change

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/mmu-arcv2.h   | 94 ++
 arch/arc/include/asm/mmu.h | 72 +--
 arch/arc/include/asm/mmu_context.h |  1 +
 arch/arc/include/asm/pgtable.h |  6 --
 arch/arc/mm/tlbex.S|  2 +-
 5 files changed, 97 insertions(+), 78 deletions(-)
 create mode 100644 arch/arc/include/asm/mmu-arcv2.h

diff --git a/arch/arc/include/asm/mmu-arcv2.h b/arch/arc/include/asm/mmu-arcv2.h
new file mode 100644
index ..837a54e39539
--- /dev/null
+++ b/arch/arc/include/asm/mmu-arcv2.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. 
(www.synopsys.com)
+ *
+ * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software 
managed.
+ * This file contains the TLB access registers and commands
+ */
+
+#ifndef _ASM_ARC_MMU_ARCV2_H
+#define _ASM_ARC_MMU_ARCV2_H
+
+/*
+ * TLB Management regs
+ */
+#define ARC_REG_MMU_BCR0x06f
+
+#ifdef CONFIG_ARC_MMU_V3
+#define ARC_REG_TLBPD0 0x405
+#define ARC_REG_TLBPD1 0x406
+#define ARC_REG_TLBPD1HI   0   /* Dummy: allows common code */
+#define ARC_REG_TLBINDEX   0x407
+#define ARC_REG_TLBCOMMAND 0x408
+#define ARC_REG_PID0x409
+#define ARC_REG_SCRATCH_DATA0  0x418
+#else
+#define ARC_REG_TLBPD0 0x460
+#define ARC_REG_TLBPD1 0x461
+#define ARC_REG_TLBPD1HI   0x463
+#define ARC_REG_TLBINDEX   0x464
+#define ARC_REG_TLBCOMMAND 0x465
+#define ARC_REG_PID0x468
+#define ARC_REG_SCRATCH_DATA0  0x46c
+#endif
+
+/* Bits in MMU PID reg */
+#define __TLB_ENABLE   (1 << 31)
+#define __PROG_ENABLE  (1 << 30)
+#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
+
+/* Bits in TLB Index reg */
+#define TLB_LKUP_ERR   0x8000
+
+#ifdef CONFIG_ARC_MMU_V3
+#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x0001)
+#else
+#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x4000)
+#endif
+
+/*
+ * TLB Commands
+ */
+#define TLBWrite   0x1
+#define TLBRead0x2
+#define TLBGetIndex0x3
+#define TLBProbe   0x4
+#define TLBWriteNI 0x5  /* write JTLB without inv uTLBs */
+#define TLBIVUTLB  0x6  /* explicitly inv uTLBs */
+
+#ifdef CONFIG_ARC_MMU_V4
+#define TLBInsertEntry 0x7
+#define TLBDeleteEntry 0x8
+#endif
+
+/* Masks for actual TLB "PD"s */
+#define PTE_BITS_IN_PD0(_PAGE_GLOBAL | _PAGE_PRESENT | 
_PAGE_HW_SZ)
+#define PTE_BITS_RWX   (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
+
+#define PTE_BITS_NON_RWX_IN_PD1(PAGE_MASK_PHYS | _PAGE_CACHEABLE)
+
+#ifndef __ASSEMBLY__
+
+extern int pae40_exist_but_not_enab(void);
+
+static inline int is_pae40_enabled(void)
+{
+   return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
+}
+
+static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
+{
+   write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
+}
+
+static void inline mmu_setup_pgd(struct mm_struct *mm, pgd_t *pgd)
+{
+   /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
+#ifdef CONFIG_ISA_ARCV2
+   write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
+#endif
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 2cabdfaf2afb..6a27a4caa44c 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -7,83 +7,13 @@
 #define _ASM_ARC_MMU_H
 
 #ifndef __ASSEMBLY__
-#include  /* NR_CPUS */
-#endif
-
-/* MMU Management regs */
-#define ARC_REG_MMU_BCR0x06f
-
-#ifdef CONFIG_ARC_MMU_V3
-#define ARC_REG_TLBPD0 0x405
-#define ARC_REG_TLBPD1 0x406
-#define ARC_REG_TLBPD1HI   0   /* Dummy: allows code sharing with 
ARC700 */
-#define ARC_REG_TLBINDEX   0x407
-#define ARC_REG_TLBCOMMAND 0x408
-#define ARC_REG_PID0x409
-#define ARC_REG_SCRATCH_DATA0  0x418
-#else
-#define ARC_REG_TLBPD0 0x460
-#define ARC_REG_TLBPD1 0x461
-#define ARC_REG_TLBPD1HI   0x463
-#define ARC_REG_TLBINDEX   0x464
-#define ARC_REG_TLBCOMMAND 0x465
-#define ARC_REG_PID0x468
-#define ARC_REG_SCRATCH_DATA0  0x46c
-#endif
-
-/* Bits in MMU PID register */
-#define __TLB_ENABLE   (1 << 31)
-#define __PROG_ENABLE  (1 << 30)
-#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
-
-/* Error code if probe fails */
-#define TLB_LKUP_ERR   0x8000
-
-#ifdef CONFIG_ARC_MMU_V3
-#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x0001)
-#else
-#define TLB_DUP_ERR(TLB_LKUP_ERR | 0x4000)
-#endif
 
-/* TLB Commands */
-#define TLBWrite0x1
-#define TLBRead 0x2
-#define TLBGetIndex 0x3
-#define TLBProbe0x4
-#define TLBWriteNI  0x5/* write JTLB witho

[PATCH 05/18] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/mm/tlb.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 6079dfd129b9..15cbc285b0de 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -71,7 +71,7 @@ static void tlb_entry_erase(unsigned int vaddr_n_asid)
}
 }
 
-static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
+static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
 {
unsigned int idx;
 
@@ -109,13 +109,16 @@ static void tlb_entry_erase(unsigned int vaddr_n_asid)
write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
 }
 
-static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
+static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
 {
write_aux_reg(ARC_REG_TLBPD0, pd0);
-   write_aux_reg(ARC_REG_TLBPD1, pd1);
 
-   if (is_pae40_enabled())
+   if (!is_pae40_enabled()) {
+   write_aux_reg(ARC_REG_TLBPD1, pd1);
+   } else {
+   write_aux_reg(ARC_REG_TLBPD1, pd1 & 0x);
write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
+   }
 
write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
 }
@@ -391,7 +394,7 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
unsigned long flags;
unsigned int asid_or_sasid, rwx;
unsigned long pd0;
-   pte_t pd1;
+   phys_addr_t pd1;
 
/*
 * create_tlb() assumes that current->mm == vma->mm, since
-- 
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[PATCH 04/18] ARC: mm: remove pgd_offset_fast

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgtable.h | 23 ---
 arch/arc/mm/fault.c|  2 +-
 2 files changed, 1 insertion(+), 24 deletions(-)

diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 0c3e220bd2b4..80b57c14b430 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -284,29 +284,6 @@ static inline void set_pte_at(struct mm_struct *mm, 
unsigned long addr,
set_pte(ptep, pteval);
 }
 
-/*
- * Macro to quickly access the PGD entry, utlising the fact that some
- * arch may cache the pointer to Page Directory of "current" task
- * in a MMU register
- *
- * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
- * becomes read a register
- *
- * CAUTION***:
- * Kernel code might be dealing with some mm_struct of NON "current"
- * Thus use this macro only when you are certain that "current" is current
- * e.g. when dealing with signal frame setup code etc
- */
-#ifdef ARC_USE_SCRATCH_REG
-#define pgd_offset_fast(mm, addr)  \
-({ \
-   pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0);  \
-   pgd_base + pgd_index(addr); \
-})
-#else
-#define pgd_offset_fast(mm, addr)  pgd_offset(mm, addr)
-#endif
-
 extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
  pte_t *ptep);
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index f5657cb68e4f..41f154320964 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -33,7 +33,7 @@ noinline static int handle_kernel_vaddr_fault(unsigned long 
address)
pud_t *pud, *pud_k;
pmd_t *pmd, *pmd_k;
 
-   pgd = pgd_offset_fast(current->active_mm, address);
+   pgd = pgd_offset(current->active_mm, address);
pgd_k = pgd_offset_k(address);
 
if (!pgd_present(*pgd_k))
-- 
2.25.1


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[PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/page.h| 30 --
 arch/arc/include/asm/pgalloc.h |  7 ++-
 2 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index c4ac827379cd..313e6f543d2d 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -34,6 +34,13 @@ void copy_user_highpage(struct page *to, struct page *from,
unsigned long u_vaddr, struct vm_area_struct *vma);
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
 
+typedef struct {
+   unsigned long pgd;
+} pgd_t;
+
+#define pgd_val(x) ((x).pgd)
+#define __pgd(x)   ((pgd_t) { (x) })
+
 typedef struct {
 #ifdef CONFIG_ARC_HAS_PAE40
unsigned long long pte;
@@ -41,22 +48,17 @@ typedef struct {
unsigned long pte;
 #endif
 } pte_t;
-typedef struct {
-   unsigned long pgd;
-} pgd_t;
+
+#define pte_val(x) ((x).pte)
+#define __pte(x)   ((pte_t) { (x) })
+
 typedef struct {
unsigned long pgprot;
 } pgprot_t;
 
-#define pte_val(x)  ((x).pte)
-#define pgd_val(x)  ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)((pte_t) { (x) })
-#define __pgd(x)((pgd_t) { (x) })
-#define __pgprot(x) ((pgprot_t) { (x) })
-
-#define pte_pgprot(x) __pgprot(pte_val(x))
+#define pgprot_val(x)  ((x).pgprot)
+#define __pgprot(x)((pgprot_t) { (x) })
+#define pte_pgprot(x)  __pgprot(pte_val(x))
 
 typedef pte_t * pgtable_t;
 
@@ -96,8 +98,8 @@ extern int pfn_valid(unsigned long pfn);
  * virt here means link-address/program-address as embedded in object code.
  * And for ARC, link-addr = physical address
  */
-#define __pa(vaddr)  ((unsigned long)(vaddr))
-#define __va(paddr)  ((void *)((unsigned long)(paddr)))
+#define __pa(vaddr)((unsigned long)(vaddr))
+#define __va(paddr)((void *)((unsigned long)(paddr)))
 
 #define virt_to_page(kaddr)pfn_to_page(virt_to_pfn(kaddr))
 #define virt_addr_valid(kaddr)  pfn_valid(virt_to_pfn(kaddr))
diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index 356237b9c537..0cf73431eb89 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -29,6 +29,11 @@
 #ifndef _ASM_ARC_PGALLOC_H
 #define _ASM_ARC_PGALLOC_H
 
+/*
+ * For ARC, pgtable_t is not struct page *, but pte_t * (to avoid
+ * extraneous page_address() calculations) hence can't use
+ * use asm-generic/pgalloc.h which assumes it being struct page *
+ */
 #include 
 #include 
 
@@ -36,7 +41,7 @@ static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 {
/*
-* The cast to long below is OK even when pte is long long (PAE40)
+* The cast to long below is OK in 32-bit PAE40 regime with long long 
pte
 * Despite "wider" pte, the pte table needs to be in non-PAE low memory
 * as all higher levels can only hold long pointers.
 *
-- 
2.25.1


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[PATCH 00/18] ARC mm updates to support 3 or 4 levels of paging

2021-08-10 Thread Vineet Gupta
Hi,

Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from
current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based
cores).

Most of these changes are incremental cleanups to make way for 14/18 and
15/18 which actually imeplement the new levels (in existing ARCv2 port)
and worth a critical eye.

CC'ing some of you guys dealing with page tables for a while :-)
to spot any obvious gotchas.

Thx,
-Vineet

Vineet Gupta (18):
  ARC: mm: simplify mmu scratch register assingment to mmu needs
  ARC: mm: remove tlb paranoid code
  ARC: mm: move mmu/cache externs out to setup.h
  ARC: mm: remove pgd_offset_fast
  ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS
  ARC: mm: Enable STRICT_MM_TYPECHECKS
  ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag
  ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)
  ARC: mm: non-functional code cleanup ahead of 3 levels
  ARC: mm: move MMU specific bits out of ASID allocator
  ARC: mm: move MMU specific bits out of entry code
  ARC: mm: disintegrate mmu.h (arcv2 bits out)
  ARC: mm: disintegrate pgtable.h into levels and flags
  ARC: mm: hack to allow 2 level build with 4 level code
  ARC: mm: support 3 levels of page tables
  ARC: mm: support 4 levels of page tables
  ARC: mm: vmalloc sync from kernel to user table to update PMD ...
  ARC: mm: introduce _PAGE_TABLE to explicitly link pgd,pud,pmd entries

 arch/arc/Kconfig  |   7 +-
 arch/arc/include/asm/cache.h  |   4 -
 arch/arc/include/asm/entry-compact.h  |   8 -
 arch/arc/include/asm/mmu-arcv2.h  |  94 +++
 arch/arc/include/asm/mmu.h|  73 +
 arch/arc/include/asm/mmu_context.h|  29 +-
 arch/arc/include/asm/page.h   |  72 +++--
 arch/arc/include/asm/pgalloc.h|  70 -
 arch/arc/include/asm/pgtable-bits-arcv2.h | 151 +++
 arch/arc/include/asm/pgtable-levels.h | 179 
 arch/arc/include/asm/pgtable.h| 315 +-
 arch/arc/include/asm/processor.h  |   2 +-
 arch/arc/include/asm/setup.h  |  12 +-
 arch/arc/kernel/entry.S   |   6 -
 arch/arc/mm/fault.c   |  20 +-
 arch/arc/mm/ioremap.c |   3 +-
 arch/arc/mm/tlb.c |  71 ++---
 arch/arc/mm/tlbex.S   |  80 ++
 18 files changed, 617 insertions(+), 579 deletions(-)
 create mode 100644 arch/arc/include/asm/mmu-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-bits-arcv2.h
 create mode 100644 arch/arc/include/asm/pgtable-levels.h

-- 
2.25.1


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[PATCH 02/18] ARC: mm: remove tlb paranoid code

2021-08-10 Thread Vineet Gupta
This was used way back when in arc700 debugging when ASID allocator was
still bit flaky. Not needed in last 5 years

Signed-off-by: Vineet Gupta 
Signed-off-by: Vineet Gupta 
---
 arch/arc/Kconfig   |  3 ---
 arch/arc/include/asm/mmu.h |  6 -
 arch/arc/mm/tlb.c  | 40 --
 arch/arc/mm/tlbex.S| 50 --
 4 files changed, 99 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 0680b1de0fc3..59d5b2a179f6 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -537,9 +537,6 @@ config ARC_DW2_UNWIND
  If you don't debug the kernel, you can say N, but we may not be able
  to solve problems without frame unwind information
 
-config ARC_DBG_TLB_PARANOIA
-   bool "Paranoia Checks in Low Level TLB Handlers"
-
 config ARC_DBG_JUMP_LABEL
bool "Paranoid checks in Static Keys (jump labels) code"
depends on JUMP_LABEL
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 4065335a7922..38a036508699 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -64,12 +64,6 @@ typedef struct {
unsigned long asid[NR_CPUS];/* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
-#else
-#define tlb_paranoid_check(a, b)
-#endif
-
 void arc_mmu_init(void);
 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
 void read_decode_mmu_bcr(void);
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 349fb7a75d1d..6079dfd129b9 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -400,7 +400,6 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
 *
 * Removing the assumption involves
 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
-* -Fix the TLB paranoid debug code to not trigger false negatives.
 * -More importantly it makes this handler inconsistent with fast-path
 *  TLB Refill handler which always deals with "current"
 *
@@ -423,8 +422,6 @@ void create_tlb(struct vm_area_struct *vma, unsigned long 
vaddr, pte_t *ptep)
 
local_irq_save(flags);
 
-   tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr);
-
vaddr &= PAGE_MASK;
 
/* update this PTE credentials */
@@ -818,40 +815,3 @@ void do_tlb_overlap_fault(unsigned long cause, unsigned 
long address,
 
local_irq_restore(flags);
 }
-
-/***
- * Diagnostic Routines
- *  -Called from Low Level TLB Handlers if things don;t look good
- **/
-
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-
-/*
- * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
- * don't match
- */
-void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
-{
-   pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
-  is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
-
-   __asm__ __volatile__("flag 1");
-}
-
-void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
-{
-   unsigned int mmu_asid;
-
-   mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
-
-   /*
-* At the time of a TLB miss/installation
-*   - HW version needs to match SW version
-*   - SW needs to have a valid ASID
-*/
-   if (addr < 0x7000 &&
-   ((mm_asid == MM_CTXT_NO_ASID) ||
- (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK
-   print_asid_mismatch(mm_asid, mmu_asid, 0);
-}
-#endif
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index bcd2909c691f..0b4bb62fa0ab 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -93,11 +93,6 @@ ex_saved_reg1:
st_s  r1, [r0, 4]
st_s  r2, [r0, 8]
st_s  r3, [r0, 12]
-
-   ; VERIFY if the ASID in MMU-PID Reg is same as
-   ; one in Linux data structures
-
-   tlb_paranoid_check_asm
 .endm
 
 .macro TLBMISS_RESTORE_REGS
@@ -146,51 +141,6 @@ ex_saved_reg1:
 
 #endif
 
-;
-;  Troubleshooting Stuff
-;
-
-; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
-; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
-; we use the MMU PID Reg to get current ASID.
-; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
-; So we try to detect this in TLB Mis shandler
-
-.macro tlb_paranoid_check_asm
-
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-
-   GET_CURR_TASK_ON_CPU  r3
-   ld r0, [r3, TASK_ACT_MM]
-   ld r0, [

[PATCH 08/18] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)

2021-08-10 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/pgalloc.h | 21 ++---
 arch/arc/include/asm/pgtable.h |  6 --
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h
index a32ca3104ced..356237b9c537 100644
--- a/arch/arc/include/asm/pgalloc.h
+++ b/arch/arc/include/asm/pgalloc.h
@@ -33,16 +33,23 @@
 #include 
 
 static inline void
-pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 {
-   pmd_set(pmd, pte);
+   /*
+* The cast to long below is OK even when pte is long long (PAE40)
+* Despite "wider" pte, the pte table needs to be in non-PAE low memory
+* as all higher levels can only hold long pointers.
+*
+* The cast itself is needed given simplistic definition of set_pmd()
+*/
+   set_pmd(pmdp, __pmd((unsigned long)ptep));
 }
 
-static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t ptep)
-{
-   pmd_set(pmd, (pte_t *) ptep);
-}
+/*
+ * pmd_populate can be implemented in terms of pmd_populate_kernel since
+ * pgtable_t is pte * on ARC
+ */
+#define pmd_populate(mm, pmdp, ptep)   pmd_populate_kernel(mm, pmdp, ptep)
 
 static inline int __get_order_pgd(void)
 {
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index b054c14f8bf6..f762bacb2358 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -222,12 +222,6 @@ extern char empty_zero_page[PAGE_SIZE];
 /* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
 #define pmd_page_vaddr(pmd)(pmd_val(pmd) & PAGE_MASK)
 
-/* In a 2 level sys, setup the PGD entry with PTE value */
-static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
-{
-   pmd_val(*pmdp) = (unsigned long)ptep;
-}
-
 #define pte_none(x)(!pte_val(x))
 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
 #define pte_clear(mm, addr, ptep)  set_pte_at(mm, addr, ptep, __pte(0))
-- 
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[PATCH 01/18] ARC: mm: simplify mmu scratch register assingment to mmu needs

2021-08-10 Thread Vineet Gupta
ARC700 SMP uses MMU scratch reg for re-entrant interrupt handling (as
opposed to the canonical usage for task pgd pointer caching for ARCv2
and ARC700 UP builds). However this requires fabricating a #define in a
header which has usual issues of dependency nesting and ugliness.

So clean this up and just use it as intended for ARCv2 only.
For ARC700 just don't use it for mmu needs (even for UP which it
potentially can (degrades it slightly) but that config it not a
big deal in this day and age.

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/entry-compact.h | 8 
 arch/arc/include/asm/mmu.h   | 4 
 arch/arc/include/asm/mmu_context.h   | 2 +-
 arch/arc/mm/tlb.c| 4 ++--
 arch/arc/mm/tlbex.S  | 2 +-
 5 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 6dbf5cecc8cc..5aab4f93ab8a 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -126,19 +126,11 @@
  * to be saved again on kernel mode stack, as part of pt_regs.
  *-*/
 .macro PROLOG_FREEUP_REG   reg, mem
-#ifndef ARC_USE_SCRATCH_REG
-   sr  \reg, [ARC_REG_SCRATCH_DATA0]
-#else
st  \reg, [\mem]
-#endif
 .endm
 
 .macro PROLOG_RESTORE_REG  reg, mem
-#ifndef ARC_USE_SCRATCH_REG
-   lr  \reg, [ARC_REG_SCRATCH_DATA0]
-#else
ld  \reg, [\mem]
-#endif
 .endm
 
 /*--
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index a81d1975866a..4065335a7922 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -31,10 +31,6 @@
 #define ARC_REG_SCRATCH_DATA0  0x46c
 #endif
 
-#if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
-#defineARC_USE_SCRATCH_REG
-#endif
-
 /* Bits in MMU PID register */
 #define __TLB_ENABLE   (1 << 31)
 #define __PROG_ENABLE  (1 << 30)
diff --git a/arch/arc/include/asm/mmu_context.h 
b/arch/arc/include/asm/mmu_context.h
index df164066e172..49318a126879 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -146,7 +146,7 @@ static inline void switch_mm(struct mm_struct *prev, struct 
mm_struct *next,
 */
cpumask_set_cpu(cpu, mm_cpumask(next));
 
-#ifdef ARC_USE_SCRATCH_REG
+#ifdef CONFIG_ISA_ARCV2
/* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
 #endif
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 8696829d37c0..349fb7a75d1d 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -719,8 +719,8 @@ void arc_mmu_init(void)
/* Enable the MMU */
write_aux_reg(ARC_REG_PID, MMU_ENABLE);
 
-   /* In smp we use this reg for interrupt 1 scratch */
-#ifdef ARC_USE_SCRATCH_REG
+   /* In arc700/smp needed for re-entrant interrupt handling */
+#ifdef CONFIG_ISA_ARCV2
/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
 #endif
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 96c3a5de9dd4..bcd2909c691f 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -202,7 +202,7 @@ ex_saved_reg1:
 
lr  r2, [efa]
 
-#ifdef ARC_USE_SCRATCH_REG
+#ifdef CONFIG_ISA_ARCV2
lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
 #else
GET_CURR_TASK_ON_CPU  r1
-- 
2.25.1


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[GIT PULL] ARC updates for 5.14-rc6

2021-08-10 Thread Vineet Gupta

Hi Linus,

ARC fixes for 5.14-rc6. Please pull.

Thx,
-Vineet

>
The following changes since commit c500bee1c5b2f1d59b1081ac879d73268ab0ff17:

  Linux 5.14-rc4 (2021-08-01 17:04:17 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ 
tags/arc-5.14-rc6


for you to fetch changes up to 669d94219d91a2ba950bb12ece69cf0ada53ad4f:

  MAINTAINERS: update Vineet's email address (2021-08-09 15:17:14 -0700)


ARC updates for 5.14-rc6

 - Fix FPU_STATUS update

 - Update my email address

 - Other spellos and fixes


Colin Ian King (1):
  arc: Fix spelling mistake and grammar in Kconfig

Guenter Roeck (1):
  ARC: Fix CONFIG_STACKDEPOT

Jinchao Wang (1):
  arc: Prefer unsigned int to bare use of unsigned

Vineet Gupta (2):
  ARC: fp: set FPU_STATUS.FWE to enable FPU_STATUS update on 
context switch

  MAINTAINERS: update Vineet's email address

 MAINTAINERS   |  2 +-
 arch/arc/Kconfig  |  2 +-
 arch/arc/include/asm/checksum.h   |  2 +-
 arch/arc/include/asm/perf_event.h |  2 +-
 arch/arc/kernel/fpu.c |  9 ++---
 arch/arc/kernel/unwind.c  | 10 +-
 arch/arc/kernel/vmlinux.lds.S |  2 ++
 7 files changed, 17 insertions(+), 12 deletions(-)

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Re: [arc:topic-mmu 27/32] arch/arc/include/asm/hugepage.h:29:36: error: implicit declaration of function 'pte_mknotpresent'; did you mean 'pte_present'?

2021-08-06 Thread Vineet Gupta
   29 | #define pmd_mkinvalid(pmd) pte_pmd(pte_mknotpresent(pmd_pte(pmd)))
>   |^~~~
> mm/pgtable-generic.c:197:49: note: in expansion of macro 'pmd_mkinvalid'
>   197 |  pmd_t old = pmdp_establish(vma, address, pmdp, 
> pmd_mkinvalid(*pmdp));
>   | ^
>>> arch/arc/include/asm/hugepage.h:29:36: error: incompatible type for 
>>> argument 1 of 'pte_pmd'
>29 | #define pmd_mkinvalid(pmd) pte_pmd(pte_mknotpresent(pmd_pte(pmd)))
>   |^~
>   ||
>   |int
> mm/pgtable-generic.c:197:49: note: in expansion of macro 'pmd_mkinvalid'
>   197 |  pmd_t old = pmdp_establish(vma, address, pmdp, 
> pmd_mkinvalid(*pmdp));
>   | ^~~~~
> arch/arc/include/asm/hugepage.h:18:35: note: expected 'pte_t' but 
> argument is of type 'int'
>18 | static inline pmd_t pte_pmd(pte_t pte)
>   | ~~^~~
> cc1: some warnings being treated as errors
>
>
> vim +29 arch/arc/include/asm/hugepage.h
>
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  22
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  23  #define pmd_wrprotect(pmd)   
> pte_pmd(pte_wrprotect(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  24  #define pmd_mkwrite(pmd) 
> pte_pmd(pte_mkwrite(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  25  #define pmd_mkdirty(pmd) 
> pte_pmd(pte_mkdirty(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  26  #define pmd_mkold(pmd)   
> pte_pmd(pte_mkold(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  27  #define pmd_mkyoung(pmd) 
> pte_pmd(pte_mkyoung(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  28  #define pmd_mkhuge(pmd)  
>     pte_pmd(pte_mkhuge(pmd_pte(pmd)))
> 86ec2da037b854 Anshuman Khandual 2020-06-03 @29  #define pmd_mkinvalid(pmd)   
> pte_pmd(pte_mknotpresent(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  30  #define pmd_mkclean(pmd) 
> pte_pmd(pte_mkclean(pmd_pte(pmd)))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  31
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  32  #define pmd_write(pmd)   
> pte_write(pmd_pte(pmd))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  33  #define pmd_young(pmd)   
> pte_young(pmd_pte(pmd))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  34  #define pmd_pfn(pmd) 
> pte_pfn(pmd_pte(pmd))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  35  #define pmd_dirty(pmd)   
> pte_dirty(pmd_pte(pmd))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  36
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  37  #define mk_pmd(page, prot)   
> pte_pmd(mk_pte(page, prot))
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  38
> fe6c1b8611aa3a Vineet Gupta  2014-07-08 @39  #define pmd_trans_huge(pmd)  
> (pmd_val(pmd) & _PAGE_HW_SZ)
> fe6c1b8611aa3a Vineet Gupta  2014-07-08  40
>
> :: The code at line 29 was first introduced by commit
> :: 86ec2da037b85436b63afe3df43ed48fa0e52b0e mm/thp: rename 
> pmd_mknotpresent() as pmd_mkinvalid()
>
> :: TO: Anshuman Khandual 
> :: CC: Linus Torvalds 
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://urldefense.com/v3/__https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org__;!!A4F2R9G_pg!JkynKBqZimbhej1a4Vdszp5CSFVPGZRDksLBzwDbrZhdmsyGKSOySAh_3SyjWe_B$


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Re: [RFC] bitops/non-atomic: make @nr unsigned to avoid any DIV

2021-08-06 Thread Vineet Gupta
On 8/6/21 6:42 AM, Will Deacon wrote:
> On Thu, Aug 05, 2021 at 12:14:08PM -0700, Vineet Gupta wrote:
>> signed math causes generation of costlier instructions such as DIV when
>> they could be done by barrerl shifter.
>>
>> Worse part is this is not caught by things like bloat-o-meter since
>> instruction length / symbols are typically same size.
>>
>> e.g.
>>
>> stock (signed math)
>> __
>>
>> 919b4614 :
>> 919b4614:div r2,r0,0x20
>>  ^^^
>> 919b4618:add2r2,0x920f6050,r2
>> 919b4620:ld_sr2,[r2,0]
>> 919b4622:lsr r0,r2,r0
>> 919b4626:j_s.d   [blink]
>> 919b4628:bmsk_s  r0,r0,0
>> 919b462a:nop_s
>>
>> (patched) unsigned math
>> __
>>
>> 919b4614 :
>> 919b4614:lsr r2,r0,0x5  @nr/32
>>  ^^^
>> 919b4618:add2r2,0x920f6050,r2
>> 919b4620:ld_sr2,[r2,0]
>> 919b4622:lsr r0,r2,r0 #test_bit()
>> 919b4626:j_s.d   [blink]
>> 919b4628:bmsk_s  r0,r0,0
>> 919b462a:nop_s
> Just FYI, but on arm64 the existing codegen is alright as we have both
> arithmetic and logical shifts.

ARC does too: There's LSR (Logical shift right) and ASR (Arithmetic 
Shift Right).
So perhaps something to be done in the compiler.

>> Signed-off-by: Vineet Gupta 
>> ---
>> This is an RFC for feeback, I understand this impacts every arch,
>> but as of now it is only buld/run tested on ARC.
>> ---
>> ---
>>   include/asm-generic/bitops/non-atomic.h | 14 +++---
>>   1 file changed, 7 insertions(+), 7 deletions(-)
> Acked-by: Will Deacon 
>
> We should really move test_bit() into the atomic header, but I failed to fix
> the resulting include mess last time I tried that.

OK I'll give it a try too.
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[RFC] bitops/non-atomic: make @nr unsigned to avoid any DIV

2021-08-05 Thread Vineet Gupta
signed math causes generation of costlier instructions such as DIV when
they could be done by barrerl shifter.

Worse part is this is not caught by things like bloat-o-meter since
instruction length / symbols are typically same size.

e.g.

stock (signed math)
__

919b4614 :
919b4614:   div r2,r0,0x20
^^^
919b4618:   add2r2,0x920f6050,r2
919b4620:   ld_sr2,[r2,0]
919b4622:   lsr r0,r2,r0
919b4626:   j_s.d   [blink]
919b4628:   bmsk_s  r0,r0,0
919b462a:   nop_s

(patched) unsigned math
__

919b4614 :
919b4614:   lsr r2,r0,0x5  @nr/32
^^^
919b4618:   add2r2,0x920f6050,r2
919b4620:   ld_sr2,[r2,0]
919b4622:   lsr r0,r2,r0 #test_bit()
919b4626:   j_s.d   [blink]
919b4628:   bmsk_s  r0,r0,0
919b462a:   nop_s

Signed-off-by: Vineet Gupta 
---
This is an RFC for feeback, I understand this impacts every arch,
but as of now it is only buld/run tested on ARC.
---
---
 include/asm-generic/bitops/non-atomic.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/asm-generic/bitops/non-atomic.h 
b/include/asm-generic/bitops/non-atomic.h
index 7e10c4b50c5d..c5a7d8eb9c2b 100644
--- a/include/asm-generic/bitops/non-atomic.h
+++ b/include/asm-generic/bitops/non-atomic.h
@@ -13,7 +13,7 @@
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
-static inline void __set_bit(int nr, volatile unsigned long *addr)
+static inline void __set_bit(unsigned int nr, volatile unsigned long *addr)
 {
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
@@ -21,7 +21,7 @@ static inline void __set_bit(int nr, volatile unsigned long 
*addr)
*p  |= mask;
 }
 
-static inline void __clear_bit(int nr, volatile unsigned long *addr)
+static inline void __clear_bit(unsigned int nr, volatile unsigned long *addr)
 {
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
@@ -38,7 +38,7 @@ static inline void __clear_bit(int nr, volatile unsigned long 
*addr)
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
-static inline void __change_bit(int nr, volatile unsigned long *addr)
+static inline void __change_bit(unsigned int nr, volatile unsigned long *addr)
 {
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
@@ -55,7 +55,7 @@ static inline void __change_bit(int nr, volatile unsigned 
long *addr)
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
-static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_set_bit(unsigned int nr, volatile unsigned long 
*addr)
 {
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
@@ -74,7 +74,7 @@ static inline int __test_and_set_bit(int nr, volatile 
unsigned long *addr)
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
-static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_clear_bit(unsigned int nr, volatile unsigned long 
*addr)
 {
unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
@@ -85,7 +85,7 @@ static inline int __test_and_clear_bit(int nr, volatile 
unsigned long *addr)
 }
 
 /* WARNING: non atomic and it can be reordered! */
-static inline int __test_and_change_bit(int nr,
+static inline int __test_and_change_bit(unsigned int nr,
volatile unsigned long *addr)
 {
unsigned long mask = BIT_MASK(nr);
@@ -101,7 +101,7 @@ static inline int __test_and_change_bit(int nr,
  * @nr: bit number to test
  * @addr: Address to start counting from
  */
-static inline int test_bit(int nr, const volatile unsigned long *addr)
+static inline int test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
 }
-- 
2.25.1


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Re: [PATCH 00/11] ARC atomics update

2021-08-05 Thread Vineet Gupta
On 8/5/21 2:02 AM, Peter Zijlstra wrote:
> On Wed, Aug 04, 2021 at 12:15:43PM -0700, Vineet Gupta wrote:
> 
>> Vineet Gupta (10):
>>ARC: atomics: disintegrate header
>>ARC: atomic: !LLSC: remove hack in atomic_set() for for UP
>>ARC: atomic: !LLSC: use int data type consistently
>>ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return
>>ARC: atomics: implement relaxed variants
>>ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines
>>ARC: xchg: !LLSC: remove UP micro-optimization/hack
>>ARC: cmpxchg/xchg: rewrite as macros to make type safe
>>ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only)
>>ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants
>>
>> Will Deacon (1):
>>ARC: switch to generic bitops
> 
> Didn't see any weird things:
> 
> Acked-by: Peter Zijlstra (Intel) 

Thx Peter. A lot of this is your code anyways ;-)

Any initial thoughts/comments on patch 06/11 - is there an obvious 
reason that generic bitops take signed @nr or the hurdle is need to be 
done consistently cross-arch.

-Vineet
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[PATCH 00/11] ARC atomics update

2021-08-04 Thread Vineet Gupta
Hi,

This series contains long due update to ARC atomics, discussed back
in 2018 [1] and [2]. I had them for arc64 port and decided to post them
here for some review and inclusion, after Mark's rework.

The main changes are use of relaxed atomics and generic bitops. Latter
does cause some cogen bloat on ARC due to signed args but that can be
reviewd seperately consider cross-arch impact.

The changes survive glibc testsuite with no regressions whatsoever.

Please review and provide any feedback.

Thx,
-Vineet

[1] 
https://lore.kernel.org/r/20180830144344.gw24...@hirez.programming.kicks-ass.net
[2] https://lore.kernel.org/r/20180830135749.ga13...@arm.com


Vineet Gupta (10):
  ARC: atomics: disintegrate header
  ARC: atomic: !LLSC: remove hack in atomic_set() for for UP
  ARC: atomic: !LLSC: use int data type consistently
  ARC: atomic64: LLSC: elide unused atomic_{and,or,xor,andnot}_return
  ARC: atomics: implement relaxed variants
  ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines
  ARC: xchg: !LLSC: remove UP micro-optimization/hack
  ARC: cmpxchg/xchg: rewrite as macros to make type safe
  ARC: cmpxchg/xchg: implement relaxed variants (LLSC config only)
  ARC: atomic_cmpxchg/atomic_xchg: implement relaxed variants

Will Deacon (1):
  ARC: switch to generic bitops

 arch/arc/include/asm/atomic-llsc.h |  97 ++
 arch/arc/include/asm/atomic-spinlock.h | 102 ++
 arch/arc/include/asm/atomic.h  | 444 ++---
 arch/arc/include/asm/atomic64-arcv2.h  | 250 ++
 arch/arc/include/asm/bitops.h  | 188 +--
 arch/arc/include/asm/cmpxchg.h | 233 ++---
 arch/arc/include/asm/smp.h |  14 -
 arch/arc/kernel/smp.c  |   2 -
 8 files changed, 588 insertions(+), 742 deletions(-)
 create mode 100644 arch/arc/include/asm/atomic-llsc.h
 create mode 100644 arch/arc/include/asm/atomic-spinlock.h
 create mode 100644 arch/arc/include/asm/atomic64-arcv2.h

-- 
2.25.1


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[PATCH 04/11] ARC: atomic64: LLSC: elide unused atomic_{and, or, xor, andnot}_return

2021-08-04 Thread Vineet Gupta
This is a non-functional change since those wrappers are not
used in kernel sources at all.

Link: 
http://lists.infradead.org/pipermail/linux-snps-arc/2018-August/004246.html
Suggested-by: Peter Zijlstra (Intel) 
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/atomic64-arcv2.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arc/include/asm/atomic64-arcv2.h 
b/arch/arc/include/asm/atomic64-arcv2.h
index 53996b11b551..22ef1cbb94e2 100644
--- a/arch/arc/include/asm/atomic64-arcv2.h
+++ b/arch/arc/include/asm/atomic64-arcv2.h
@@ -116,6 +116,12 @@ static inline s64 arch_atomic64_fetch_##op(s64 a, 
atomic64_t *v)   \
 
 ATOMIC64_OPS(add, add.f, adc)
 ATOMIC64_OPS(sub, sub.f, sbc)
+
+#undef ATOMIC64_OPS
+#define ATOMIC64_OPS(op, op1, op2) \
+   ATOMIC64_OP(op, op1, op2)   \
+   ATOMIC64_FETCH_OP(op, op1, op2)
+
 ATOMIC64_OPS(and, and, and)
 ATOMIC64_OPS(andnot, bic, bic)
 ATOMIC64_OPS(or, or, or)
-- 
2.25.1


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[PATCH 03/11] ARC: atomic: !LLSC: use int data type consistently

2021-08-04 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/atomic-spinlock.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/include/asm/atomic-spinlock.h 
b/arch/arc/include/asm/atomic-spinlock.h
index 8c6fd0e651e5..2c830347bfb4 100644
--- a/arch/arc/include/asm/atomic-spinlock.h
+++ b/arch/arc/include/asm/atomic-spinlock.h
@@ -42,7 +42,7 @@ static inline void arch_atomic_##op(int i, atomic_t *v)   
\
 static inline int arch_atomic_##op##_return(int i, atomic_t *v)
\
 {  \
unsigned long flags;\
-   unsigned long temp; \
+   unsigned int temp;  \
\
/*  \
 * spin lock/unlock provides the needed smp_mb() before/after   \
@@ -60,7 +60,7 @@ static inline int arch_atomic_##op##_return(int i, atomic_t 
*v)   \
 static inline int arch_atomic_fetch_##op(int i, atomic_t *v)   \
 {  \
unsigned long flags;\
-   unsigned long orig; \
+   unsigned int orig;  \
\
/*  \
 * spin lock/unlock provides the needed smp_mb() before/after   \
-- 
2.25.1


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[PATCH 09/11] ARC: cmpxchg/xchg: rewrite as macros to make type safe

2021-08-04 Thread Vineet Gupta
Existing code forces/assume args to type "long" which won't work in LP64
regime, so prepare code for that

Interestingly this should be a non functional change but I do see
some codegen changes

| bloat-o-meter vmlinux-cmpxchg-A vmlinux-cmpxchg-B
| add/remove: 0/0 grow/shrink: 17/12 up/down: 218/-150 (68)
|
| Function old new   delta
| rwsem_optimistic_spin518 550 +32
| rwsem_down_write_slowpath   12441274 +30
| __do_sys_perf_event_open25762600 +24
| down_read192 200  +8
| __down_read  192 200  +8
...
| task_work_run168 148 -20
| dma_fence_chain_walk.part760 736 -24
| __genradix_ptr_alloc 674 646 -28

Total: Before=6187409, After=6187477, chg +0.00%

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/cmpxchg.h | 209 ++---
 1 file changed, 117 insertions(+), 92 deletions(-)

diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index bac9b564a140..00deb076d6f6 100644
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -6,6 +6,7 @@
 #ifndef __ASM_ARC_CMPXCHG_H
 #define __ASM_ARC_CMPXCHG_H
 
+#include 
 #include 
 
 #include 
@@ -13,62 +14,77 @@
 
 #ifdef CONFIG_ARC_HAS_LLSC
 
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
-{
-   unsigned long prev;
-
-   /*
-* Explicit full memory barrier needed before/after as
-* LLOCK/SCOND themselves don't provide any such semantics
-*/
-   smp_mb();
-
-   __asm__ __volatile__(
-   "1: llock   %0, [%1]\n"
-   "   brne%0, %2, 2f  \n"
-   "   scond   %3, [%1]\n"
-   "   bnz 1b  \n"
-   "2: \n"
-   : "="(prev)   /* Early clobber, to prevent reg reuse */
-   : "r"(ptr), /* Not "m": llock only supports reg direct addr mode */
- "ir"(expected),
- "r"(new)  /* can't be "ir". scond can't take LIMM for "b" */
-   : "cc", "memory"); /* so that gcc knows memory is being written here */
-
-   smp_mb();
-
-   return prev;
-}
-
-#else /* !CONFIG_ARC_HAS_LLSC */
-
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
-{
-   unsigned long flags;
-   int prev;
-   volatile unsigned long *p = ptr;
-
-   /*
-* spin lock/unlock provide the needed smp_mb() before/after
-*/
-   atomic_ops_lock(flags);
-   prev = *p;
-   if (prev == expected)
-   *p = new;
-   atomic_ops_unlock(flags);
-   return prev;
-}
+/*
+ * if (*ptr == @old)
+ *  *ptr = @new
+ */
+#define __cmpxchg(ptr, old, new)   \
+({ \
+   __typeof__(*(ptr)) _prev;   \
+   \
+   __asm__ __volatile__(   \
+   "1: llock  %0, [%1] \n" \
+   "   brne   %0, %2, 2f   \n" \
+   "   scond  %3, [%1] \n" \
+   "   bnz 1b  \n" \
+   "2: \n" \
+   : "="(_prev)  /* Early clobber prevent reg reuse */   \
+   : "r"(ptr), /* Not "m": llock only supports reg */  \
+ "ir"(old),\
+ "r"(new)  /* Not "ir": scond can't take LIMM */   \
+   : "cc", \
+ "memory");/* gcc knows memory is clobbered */ \
+   \
+   _prev;  \
+})
 
-#endif
+#define arch_cmpxchg(ptr, old, new)\
+({ \
+   __typeof__(ptr) _p_ = (ptr);\
+   __typeof__(*(ptr)) _o_ = (old); \
+   __typeof__(*(ptr)) _n_

[PATCH 07/11] ARC: bitops: fls/ffs to take int (vs long) per asm-generic defines

2021-08-04 Thread Vineet Gupta
Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/bitops.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 4f35130f5ba3..a7daaf64ae34 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -114,7 +114,7 @@ static inline __attribute__ ((const)) unsigned long 
__ffs(unsigned long word)
  * @result: [1-32]
  * fls(1) = 1, fls(0x8000) = 32, fls(0) = 0
  */
-static inline __attribute__ ((const)) int fls(unsigned long x)
+static inline __attribute__ ((const)) int fls(unsigned int x)
 {
int n;
 
@@ -141,7 +141,7 @@ static inline __attribute__ ((const)) int __fls(unsigned 
long x)
  * ffs = Find First Set in word (LSB to MSB)
  * @result: [1-32], 0 if all 0's
  */
-static inline __attribute__ ((const)) int ffs(unsigned long x)
+static inline __attribute__ ((const)) int ffs(unsigned int x)
 {
int n;
 
-- 
2.25.1


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