This updates the documentation for supporting an optional extra interrupt
cell to specify edge vs level triggered.
Signed-off-by: Mischa Jonker
---
.../interrupt-controller/snps,archs-idu-intc.txt | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
index c5a1c7b..a5c1db9 100644
---
a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+++
b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -8,11 +8,20 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
-- #interrupt-cells: Must be <1>.
-
- Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
- of the particular interrupt line of IDU corresponds to the line N+24 of the
- core interrupt controller.
+- #interrupt-cells: Must be <1> or <2>.
+
+ Value of the first cell specifies the "common" IRQ from peripheral to IDU.
+ Number N of the particular interrupt line of IDU corresponds to the line N+24
+ of the core interrupt controller.
+
+ The (optional) second cell specifies any of the following flags:
+- bits[3:0] trigger type and level flags
+1 = low-to-high edge triggered
+2 = NOT SUPPORTED (high-to-low edge triggered)
+4 = active high level-sensitive <<< DEFAULT
+8 = NOT SUPPORTED (active low level-sensitive)
+ When no second cell is specified, the interrupt is assumed to be level
+ sensitive.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.
--
2.8.3
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