Re: [PATCH -next] trap: Cleanup trap_init()

Kefeng Wang writes: > There are some empty trap_init() in different ARCHs, introduce > a new weak trap_init() function to cleanup them. > > Cc: Vineet Gupta > Cc: Russell King > Cc: Yoshinori Sato > Cc: Ley Foon Tan > Cc: Jonas Bonn > Cc: Stefan Kristiansson > Cc: Stafford Horne > Cc:

[linux-next:master 5363/7554] kernel/sys.c:1896:17: sparse: sparse: incorrect type in assignment (different address spaces)

tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 9b992972fb9c2a1bc3fb25bab70da8a4385e3abe commit: 9cf1d7d830f4a586dfa4ddcaf9eae3959e0708ef [5363/7554] ARC: cmpxchg/xchg: rewrite as macros to make type safe config: arc-randconfig-s032-20210812 (attached

Re: [PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out)

Hi Vineet, I love your patch! Yet something to improve: [auto build test ERROR on arc/for-next] [also build test ERROR on next-20210812] [cannot apply to linux/master linus/master v5.14-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we

Re: [PATCH -next] trap: Cleanup trap_init()

On Thu, Aug 12, 2021 at 08:36:02PM +0800, Kefeng Wang wrote: > There are some empty trap_init() in different ARCHs, introduce > a new weak trap_init() function to cleanup them. > > Cc: Vineet Gupta > Cc: Russell King > Cc: Yoshinori Sato > Cc: Ley Foon Tan > Cc: Jonas Bonn > Cc: Stefan

[PATCH -next] trap: Cleanup trap_init()

There are some empty trap_init() in different ARCHs, introduce a new weak trap_init() function to cleanup them. Cc: Vineet Gupta Cc: Russell King Cc: Yoshinori Sato Cc: Ley Foon Tan Cc: Jonas Bonn Cc: Stefan Kristiansson Cc: Stafford Horne Cc: James E.J. Bottomley Cc: Helge Deller Cc:

Re: [PATCH -next] trap: Cleanup trap_init()

On 8/12/21 5:36 AM, Kefeng Wang wrote: There are some empty trap_init() in different ARCHs, introduce a new weak trap_init() function to cleanup them. Cc: Vineet Gupta Cc: Russell King Cc: Yoshinori Sato Cc: Ley Foon Tan Cc: Jonas Bonn Cc: Stefan Kristiansson Cc: Stafford Horne Cc: James E.J.

Re: [PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

On 8/11/21 11:18 PM, Mike Rapoport wrote: On Wed, Aug 11, 2021 at 06:37:19PM -0700, Vineet Gupta wrote: On 8/11/21 5:31 AM, Mike Rapoport wrote: +/* + * For ARC, pgtable_t is not struct page *, but pte_t * (to avoid + * extraneous page_address() calculations) hence can't use + * use

[PATCH v2 04/19] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS

Signed-off-by: Vineet Gupta --- arch/arc/mm/tlb.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 6079dfd129b9..15cbc285b0de 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -71,7 +71,7 @@ static void

[PATCH v2 02/19] ARC: mm: remove tlb paranoid code

This was used back in arc700 days when ASID allocator was fragile. Not needed in last 5 years Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 3 --- arch/arc/include/asm/mmu.h | 6 - arch/arc/mm/tlb.c | 40 -- arch/arc/mm/tlbex.S|

[PATCH v2 06/19] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag

and remove the one off uncached definition for ARC Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgtable.h | 3 --- arch/arc/mm/ioremap.c | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index

[PATCH v2 18/19] ARC: mm: vmalloc sync from kernel to user table to update PMD ...

... not PGD vmalloc() sets up the kernel page table (starting from @swapper_pg_dir). But when vmalloc area is accessed in context of a user task, say opening terminal in n_tty_open(), the user page tables need to be synced from kernel page tables so that TLB entry is created in "user context".

[PATCH v2 08/19] ARC: mm: switch pgtable_t back to struct page *

So far ARC pgtable_t has not been struct page based to avoid extra page_address() calls involved. However the differences are down to noise and get in the way of using generic code, hence this patch. Suggested-by: Mike Rapoport Signed-off-by: Vineet Gupta --- arch/arc/include/asm/page.h|

[PATCH v2 03/19] ARC: mm: move mmu/cache externs out to setup.h

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/cache.h | 4 arch/arc/include/asm/mmu.h | 4 arch/arc/include/asm/setup.h | 12 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index

[PATCH v2 10/19] ARC: mm: non-functional code cleanup ahead of 3 levels

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/page.h | 30 -- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h index 514b8b70df50..28ed82b1800f 100644 --- a/arch/arc/include/asm/page.h +++

[PATCH v2 16/19] ARC: mm: support 3 levels of page tables

ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte. Forthcoming hw will have multiple levels, so this change preps mm code for same. It is also fun to try multi levels even on soft-walked code to ensure generic mm code is robust to handle. overview 2 levels

[PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code

PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-* but only for !__ASSEMBLY__ tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs for CONFIG_PGTABLE_LEVEL={2,3} and works for 4. So add a workaround local to tlbex.S - the proper fix is to change

[PATCH v2 19/19] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd, pud, pmd entries

ARCv3 hardware walker expects Table Descriptors to have b'11 in LSB bits to continue moving to next level. This commits adds that (to ARCv2 code) and ensures that it works in software walked regime. The pte entries stil need tagging, but that is not possible in ARCv2 since the LSB 2 bits are

[PATCH v2 12/19] ARC: mm: move MMU specific bits out of entry code ...

... to avoid polluting shared entry code (across three ISA variants) with ISA/MMU specific code. Cc: Jose Abreu Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu.h| 8 arch/arc/kernel/entry-arcv2.S | 1 + arch/arc/kernel/entry.S | 7 ++- 3 files changed, 11

[PATCH v2 05/19] ARC: mm: Enable STRICT_MM_TYPECHECKS

In the past I've refrained from doing this (at least 2 times) due to the slight code bloat due to ABI implications of pte_t etc becoming struct Per ARC ABI, functions return struct via memory and not through register r0, even if the struct would fit in register(s) - caller allocates space on

[PATCH v2 09/19] ARC: mm: switch to asm-generic/pgalloc.h

With previous patch ARC pgalloc functions are same as generic, hence switch to that. Suggested-by: Mike Rapoport Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgalloc.h | 42 +- 1 file changed, 1 insertion(+), 41 deletions(-) diff --git

[PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

MMU SCRATCH_DATA0 register is intended to cache task pgd. However in ARC700 SMP port, it has to be repurposed for reentrant interrupt handling, while UP port doesn't. We currently ahandle boe usecases using a fabricated which has usual issues of dependency nesting and ugliness. So clean this up:

[PATCH v2 11/19] ARC: mm: move MMU specific bits out of ASID allocator

And while at it, rewrite commentary on ASID allocator Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu.h | 13 + arch/arc/include/asm/mmu_context.h | 28 +--- arch/arc/mm/tlb.c | 11 --- 3 files changed, 30

[PATCH v2 07/19] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgalloc.h | 14 ++ arch/arc/include/asm/pgtable.h | 6 -- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arc/include/asm/pgalloc.h b/arch/arc/include/asm/pgalloc.h index a32ca3104ced..408bc4b0842d 100644

[PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc

Hi, Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based cores). Most of these changes are incremental cleanups to make way for 14/18 and 15/18 which actually imeplement the new levels (in existing ARCv2

[PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out)

non functional change Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mmu-arcv2.h | 103 +++ arch/arc/include/asm/mmu.h | 80 +--- arch/arc/include/asm/pgtable.h | 6 -- 3 files changed, 105 insertions(+), 84 deletions(-) create

[PATCH v2 14/19] ARC: mm: disintegrate pgtable.h into levels and flags

- pgtable-bits-arcv2.h (MMU specific page table flags) - pgtable-levels.h (paging levels) No functional changes, but paves way for easy addition of new MMU code with different bits and levels etc Signed-off-by: Vineet Gupta --- arch/arc/include/asm/pgtable-bits-arcv2.h | 149

[PATCH v2 17/19] ARC: mm: support 4 levels of page tables

Signed-off-by: Vineet Gupta --- arch/arc/include/asm/page.h | 11 +++ arch/arc/include/asm/pgalloc.h| 11 +++ arch/arc/include/asm/pgtable-levels.h | 45 --- arch/arc/mm/fault.c | 2 ++ arch/arc/mm/init.c|

Re: [PATCH 09/18] ARC: mm: non-functional code cleanup ahead of 3 levels

On Wed, Aug 11, 2021 at 06:37:19PM -0700, Vineet Gupta wrote: > On 8/11/21 5:31 AM, Mike Rapoport wrote: > > > +/* > > > + * For ARC, pgtable_t is not struct page *, but pte_t * (to avoid > > > + * extraneous page_address() calculations) hence can't use > > > + * use asm-generic/pgalloc.h which