Re: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first

[Stephen Boyd]

Quoting Eugeniy Paltsev (2020-03-11 06:41:13)
> If PLL is bypassed the EN (enable) bit has no effect on
> output clock.
> 
> Signed-off-by: Eugeniy Paltsev 
> ---

Applied to clk-next

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[PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first

[Eugeniy Paltsev]

If PLL is bypassed the EN (enable) bit has no effect on
output clock.

Signed-off-by: Eugeniy Paltsev 
---
 drivers/clk/clk-hsdk-pll.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 97d1e8c35b71..b47a559f3528 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -172,14 +172,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw 
*hw,
 
dev_dbg(clk->dev, "current configuration: %#x\n", val);
 
-   /* Check if PLL is disabled */
-   if (val & CGU_PLL_CTRL_PD)
-   return 0;
-
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
return parent_rate;
 
+   /* Check if PLL is disabled */
+   if (val & CGU_PLL_CTRL_PD)
+   return 0;
+
/* input divider = reg.idiv + 1 */
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
/* fb divider = 2*(reg.fbdiv + 1) */
-- 
2.21.1


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