Hi Hans,
On Sat, Dec 21, 2013 at 01:15:07PM +0100, Hans de Goede wrote:
I think that adding a new factors calculation function for sun5i's
PLL6, that would limit the factors returned to whatever frequency is
adequate would work. Emilio?
The problem is that the clk framework will first try
Quoting Chen-Yu Tsai (2013-12-24 05:26:17)
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to module 0
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Looks good to me.
These macros are used to convert between physical addresses (as
seen by the CPU) and bus addresses (as seen by various peripherals
such as the display controller, cedar, g2d, mali, ...).
The difference between physical and bus addresses is 0x4000,
because that's the physical address of SDRAM
On Fri, 27 Dec 2013 08:04:49 -0800 (PST)
pmsc...@gmail.com wrote:
Same problem for me :-(
Thanks for reminding. This issue can be fixed by something like this:
http://thread.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/5480
I guess now the ball is more or less on the application
This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai
