Hi All,
Did any one tried of interfacing external codec to i2s of sunxi?.
Because in my case i am able to play audio , but not getting any audio in
HPL and HPR lines.
And also codec part is not through any error also.
i am getting all signals of mclk,wclk,bclk,din.
Here will be link for my
Hello zhang.
I'd like to use the two cameras at the same time.
And I'm using A10 chip.
Can you explain if you achieved improvements in this technique?
And then do you have ov7725 driver for sunxi?
Kind regards,
Ryang
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On Tue, Jun 24, 2014 at 5:59 PM, Chen-Yu Tsai w...@csie.org wrote:
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
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arch/arm/boot/dts/sun8i-a23.dtsi | 115
Hi,
Transparency layer is in fact fb layer (it's already open and init once you
start the system). In contrast, V4L2 layer is opened and initialized in
your application.
In order for everything to work there are a few things you'd need to do
(this is for fb0 - for fb1 everything is the same,
On Fri, Jun 20, 2014 at 02:13:58PM +0800, Chen-Yu Tsai wrote:
If these two clocks are these different though, maybe it would just be
easier to add a new driver. These are trivial enough anyway.
Yes it is. But it adds more of the same boilerplate code than actual
differences of the
On Tue, Jun 24, 2014 at 05:59:34PM +0800, Chen-Yu Tsai wrote:
Hi everyone,
This is a followup series to my A23 bare-minimum bringup series [1],
which adds basic clock support for the A23 SoC. It is one of many
split up from the original A23 series [2]. Yet to come are more
clocks, reset
On Tue, Jun 24, 2014 at 05:59:37PM +0800, Chen-Yu Tsai wrote:
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.
On Tue, Jun 24, 2014 at 05:59:39PM +0800, Chen-Yu Tsai wrote:
The clock control unit on the A23 is similar to the one found on the A31.
The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.
The main CPU PLL (PLL1) however is like
Maybe you are loading the DTB too close to the kernel and when the
kernel expands it over writes it
On Wed, Jun 25, 2014 at 4:37 PM, bruce bushby bruce.bus...@gmail.com wrote:
Doesn't helpwhich suggests I'm doing something fundamentally wrong.
bootargs=console=ttyS0,115200 loglevel=9
Hi Maxime
Nope... didn't think about damaging the board. I have absolutely no
idea what I'm doing :) ...it's just a hobby and I figured the only way to
learn is to try.you really don't want to watch me connecting the
breadboard LOL
I try and avoid constantly asking junior questions
Hi Bruce,
I’m just guessing here, but if you can find an A20 board that is similar to the
Olimex one you should be able to modify the DTS file so that the pin mapping is
correct for your board. You will need the schematics to find which output pins
on the CPU are routed to which peripheral.
I booting linux-3.15 on pcDuino V3(A20 onboard).
1,second CPU failed,I used https://github.com/jwrdegoede/u-boot-sunxi,then
fixed it.
2,missing clock-frequency property
The following is a useful log
[0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[0.00]
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