On Sun, Oct 12, 2014 at 12:17 AM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
Ippo q8h is a series of A23 tablet boards. This defconfig
is for v5 of these boards, though for u-boot purposes they
are mostly the same.
Any differences worth
On Sun, Oct 12, 2014 at 12:13 AM, Ian Campbell i...@hellion.org.uk wrote:
On Sat, 2014-10-11 at 17:11 +0100, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Hi,
On 10/11/2014 05:39 PM, Ian Campbell wrote:
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
I presume that adding GPIO support to SPL isn't a problem size wise?
We do link time size checking and ./MAKEALL -s sunxi still works
Hi,
On 10/11/2014 05:40 PM, Ian Campbell wrote:
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL
check is not necessary with Kconfig, because only options explicitly marked
as also being for the SPL get set
Hi,
On 10/11/2014 05:50 PM, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when
CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally
include it when CONFIG_MMC is enabled, as we do for
Hi,
On 10/11/2014 05:43 PM, Ian Campbell wrote:
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
@@ -108,11 +109,31 @@ static void mmc_pinmux_setup(int sdc)
int board_mmc_init(bd_t *bis)
{
+__maybe_unused struct mmc *mmc0, *mmc1;
+__maybe_unused char buf[512];
+
On Sun, 2014-10-12 at 10:43 +0800, Chen-Yu Tsai wrote:
On Sat, Oct 11, 2014 at 11:58 PM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and
On Sun, 2014-10-12 at 16:23 +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called
Hi everyone,
This series adds support for the basic bus (AHB/APB) clocks used by
peripherals on the A80 SoC. This series is based on my previous A80
bringup series.
The A80 has 5 peripheral related bus clocks, 1 data bus clock, and 1
CCI bus clock. 2 out of 12 PLLs are used to clock these.
Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.
Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow reuse
in case we support table-based muxes in the future.
The A80 SoC has reset controls matching bus clock gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index d04f84b..a77604f 100644
---
This adds the gate clocks for AHB/APB busses on the A80 SoC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5
drivers/clk/sunxi/clk-sunxi.c | 31 +++
2 files changed, 36 insertions(+)
diff --git
The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new GT bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.
As far as I can tell, the GT bus and CCI400 bus clock must be
Hi ChenYu,
On 10/12/2014 11:40 AM, Chen-Yu Tsai wrote:
Hi everyone,
This series adds support for the basic bus (AHB/APB) clocks used by
peripherals on the A80 SoC. This series is based on my previous A80
bringup series.
Cool stuff, any chance you could write a quick howto for getting an
Hey Siarhei,
this driver only works on 3.4 right? I think we have the axp20x driver
in mainline too do we not?
Anyway, I think in a few weeks time from now, I will run some
temperature calibration tests on various Lime's and will generate a lot
of temperature data. It won't be a huge
Hey Olliver,
For mainline I wrote a driver for the power supply part some time ago
and posted it here (it's referenced from the mainlining page on the WIKI).
It covers ACIN, BATTERY and VBUS power supplies with both current and
voltage measurements. For battery it could also provide temperature
On 05/30/2014 06:24 PM, Siarhei Siamashka wrote:
On Sun, 25 May 2014 11:43:52 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/25/2014 12:34 AM, Olliver Schinagl wrote:
Hey all,
I am just venting here mostly as I don't have much time to test things
really just yet.
As you know I am
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one mmc dev 0 so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the
Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL
check is not necessary with Kconfig, because only options explicitly marked
as also being for the SPL get set during SPL builds.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Unify the sunxi Kconfig code, instead of having seperate code blocks for
each of sun4i, sun5i and sun7i.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
board/sunxi/Kconfig | 32 +---
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git
Enable the second sdcard slot found on some boards. Note that we do not
set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful,
Except for on the Mele-M3 where the second sdcard is an eMMC, from which the
device can also boot, and there we want to have both in the SPL, so
On Sun, 2014-10-12 at 20:07 +0200, Hans de Goede wrote:
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one mmc dev 0 so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2,
On Sun, 2014-10-12 at 20:07 +0200, Hans de Goede wrote:
Unify the sunxi Kconfig code, instead of having seperate code blocks for
separate
each of sun4i, sun5i and sun7i.
Signed-off-by: Hans de Goede hdego...@redhat.com
Looks pretty familiar ;-)
Acked-by: Ian Campbell i...@hellion.org.uk
On Sun, 2014-10-12 at 20:07 +0200, Hans de Goede wrote:
Hi Ian,
Here is v3 of my second sdcard slot patch-set.
Changes since v2:
- Rebased on top of latest u-boot-sunxi-next
- Fixed Kconfig help text for : sunxi: Turn MMC_SUNXI_SLOT_EXTRA into a
proper Kconfig option to also mention
Hi,
On 10/12/2014 11:19 PM, Ian Campbell wrote:
On Sun, 2014-10-12 at 20:07 +0200, Hans de Goede wrote:
Hi Ian,
Here is v3 of my second sdcard slot patch-set.
Changes since v2:
- Rebased on top of latest u-boot-sunxi-next
- Fixed Kconfig help text for : sunxi: Turn MMC_SUNXI_SLOT_EXTRA
HI All,
I tried with vlc from below link , but having same result that video
display is not coming on second display.
http://linux-sunxi.org/VLC
Can anyone know , how to solve this. Kindly suggest me .
Regards
Punith
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