On Sun, Nov 02, 2014 at 10:28:48AM -0500, jonsm...@gmail.com wrote:
Simplefb is also being developed as a way of protecting the BIOS setup
of the framebuffer past the boot process and out into use as a normal
user space console. I in no way support this use. We have experienced
decades of
Hi Ezaul,
On Tue, 04 November 2014 Ezaul Zillmer ezaulzill...@gmail.com wrote:
Cubieboard2 + Kernel 3.18-rc3
[ 15.955655] axp20x-regulator axp20x-regulator: regulators node not found
[ 15.962580] LDO1: 1300 mV
[ 15.965732] LDO2: at 3000 mV
[ 15.969120] LDO3: at 2275 mV
[
On Wed, Nov 5, 2014 at 1:03 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Nov 04, 2014 at 12:07:16PM +0800, Chen-Yu Tsai wrote:
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
Hi,
On Tue, Nov 4, 2014 at 2:16 PM, Priit Laes pl...@plaes.org wrote:
On Tue, 2014-11-04 at 12:07 +0800, Chen-Yu Tsai wrote:
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a
different
controller.
This adds a
Hi Russell,
On Tue, Nov 04, 2014 at 06:12:19PM +, Russell King - ARM Linux wrote:
On Tue, Nov 04, 2014 at 12:07:14PM +0800, Chen-Yu Tsai wrote:
+ spin_lock_irqsave(data-lock, flags);
+
+ reg = readl(data-reg);
+ writel(reg ~BIT(id), data-reg);
+
+
On Tue, Nov 04, 2014 at 08:16:13AM +0200, Priit Laes wrote:
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -153,6 +153,18 @@ config PHY_SUN4I_USB
This driver controls the entire USB PHY
block, both the USB OTG
parts, as well as
Hi,
On Wed, Nov 5, 2014 at 12:57 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Tue, Nov 04, 2014 at 12:07:14PM +0800, Chen-Yu Tsai wrote:
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
On Wed, Nov 05, 2014 at 06:02:35PM +0800, Chen-Yu Tsai wrote:
+static void __init sunxi_usb_clk_setup(struct device_node *node,
+const struct usb_clk_data *data,
+spinlock_t *lock)
+{
+ struct clk_onecell_data
clabbe.montjoie wrote:
For the temperature value, I cannot found any document on how to transform
the raw value in °C.
[...]
Under heavy loads, the temperature of both sensors rise linearly.
But based on a series of tests with and without heatsinks applied to the A20 I
came to the
*Hello Bruno Thank you for your attention sought some more docs just
applying a patch and here is the result.*
*add*
*https://dev.openwrt.org/browser/trunk/target/linux/sunxi/patches-3.14/210-mfd-add-axp20x-pmic-driver.patch?rev=42463*
Hi,
On 11/03/2014 04:59 PM, Chen-Yu Tsai wrote:
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede hdego...@redhat.com wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the
Until some new SoC part of the sun9i family comes up, and it will just
add to the confusion.
Maybe, but then again maybe not. It depends whether such a new member
ever shows up, and whether it has a hardware that's compatible enough
that the code doesn't need to be changed (seems unlikely).
Hi Stefan,
Please keep me in Cc.
On Wed, Nov 05, 2014 at 08:27:41AM -0500, Stefan Monnier wrote:
Until some new SoC part of the sun9i family comes up, and it will just
add to the confusion.
Maybe, but then again maybe not. It depends whether such a new member
ever shows up, and whether
On Tue, Nov 04, 2014 at 10:08:27PM +0100, Bruno Prémont wrote:
On Tue, 04 November 2014 Maxime Ripard maxime.rip...@free-electrons.com
wrote:
On Mon, Nov 03, 2014 at 09:02:44PM +0100, Bruno Prémont wrote:
Doing something like this?:
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
Op 5 nov. 2014, om 15:48 heeft Maxime Ripard
maxime.rip...@free-electrons.com het volgende geschreven:
On Tue, Nov 04, 2014 at 10:08:27PM +0100, Bruno Prémont wrote:
On Tue, 04 November 2014 Maxime Ripard maxime.rip...@free-electrons.com
wrote:
On Mon, Nov 03, 2014 at 09:02:44PM +0100,
From: Andreas Baierl ich...@imkreisrum.de
Signed-off-by: Andreas Baierl ich...@imkreisrum.de
---
arch/arm/configs/sun7i_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/sun7i_defconfig b/arch/arm/configs/sun7i_defconfig
index be7fedb..ce17398
Hi,
On 11/03/2014 05:05 PM, Chen-Yu Tsai wrote:
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede hdego...@redhat.com wrote:
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/include/asm/arch-sunxi/cpu.h| 5 +++
Hi,
On 11/04/2014 05:23 AM, Julian Calaby wrote:
Hi Hans,
On Tue, Nov 4, 2014 at 2:34 AM, Hans de Goede hdego...@redhat.com wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
---
board/sunxi/board.c| 26 +++
drivers/power/Kconfig | 47
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 77
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/psci.S| 4 +-
arch/arm/include/asm/arch-sunxi/cpu.h | 3 +-
arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 67 ++
3 files
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
On Wed, Nov 5, 2014 at 6:09 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Nov 05, 2014 at 06:02:35PM +0800, Chen-Yu Tsai wrote:
+static void __init sunxi_usb_clk_setup(struct device_node *node,
+const struct usb_clk_data *data,
+
Am 05.11.2014 12:44 schrieb thomas.kai...@phg-online.de:
clabbe.montjoie wrote:
For the temperature value, I cannot found any document on how to
transform the raw value in °C.
[...]
Under heavy loads, the temperature of both sensors rise linearly.
But based on a series of tests with and
Hi, Ryong,
You can use make menuconfig, and there will be a option of choosing
wether to use arguments compiled in kernel, and you can alse specify
the arguments to use.
I have ever do this some time ago, and it boots correctly.
Hope this be of help.
Regards
2014-11-05 15:14 GMT+08:00 Ryang
On Fri, Sep 26, 2014 at 11:06:01AM +0800, Chen-Yu Tsai wrote:
On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi everyone,
This is v2 of my sun8i DMA controller support series. This series
adds support for the DMA controller found in the Allwinner A23 SoC.
It is the
On Thu, Nov 6, 2014 at 3:11 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Sep 26, 2014 at 11:06:01AM +0800, Chen-Yu Tsai wrote:
On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi everyone,
This is v2 of my sun8i DMA controller support series. This series
adds
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