[linux-sunxi] Re: [PATCH v3 01/13] pinctrl: sunxi: Add A83T R_PIO controller support

On Sat, Mar 5, 2016 at 10:42 PM, Vishnu Patekar wrote: > The A83T has R_PIO pin controller, it's same as A23, execpt A83T > interrupt bit is 6th and A83T has one extra pin PL12. > > Signed-off-by: Vishnu Patekar > Acked-by: Chen-Yu Tsai

[linux-sunxi] Re: [PATCH 4/7] scatterlist: add sg_alloc_table_from_buf() helper

Hi Laurent, On Tue, 08 Mar 2016 18:51:49 +0200 Laurent Pinchart wrote: > Hi Boris, > > Thank you for the patch. > > On Tuesday 08 March 2016 12:15:12 Boris Brezillon wrote: > > sg_alloc_table_from_buf() provides an easy solution to create an sg_table > >

[linux-sunxi] Re: [PATCH 4/7] scatterlist: add sg_alloc_table_from_buf() helper

Hi Boris, Thank you for the patch. On Tuesday 08 March 2016 12:15:12 Boris Brezillon wrote: > sg_alloc_table_from_buf() provides an easy solution to create an sg_table > from a virtual address pointer. This function takes care of dealing with > vmallocated buffers, buffer alignment, or DMA

[linux-sunxi] Re: [PATCH 02/16] mtd: nand: sunxi: fix clk rate calculation

Boris, On Mon, 7 Mar 2016 17:18:19 +0100, Boris Brezillon wrote: > Unlike what is specified in the Allwinner datasheets, the NAND clock rate > is not equal to 2/T but 1/T. Fix the clock rate selection accordingly. > > Signed-off-by: Boris Brezillon > --- >

[linux-sunxi] Re: [PATCH 5/7] mtd: provide helper to prepare buffers for DMA operations

On Tue, 8 Mar 2016 19:48:53 +0530 Vinod Koul wrote: > On Tue, Mar 08, 2016 at 12:15:13PM +0100, Boris Brezillon wrote: > > > > +#ifdef CONFIG_HAS_DMA > > Shouldn't this be CONFIG_DMA_ENGINE as you are preparing these descriptors > for DMA transfer? > Nope, scatterlist

[linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

>>> Why does dmaengine need to wait? Can you explain that [...] > I see 2 possible reasons why waiting till checking for drq can help: Any chance something similar is causing the "max 50MB/s" limit on SATA transfers for A10/A20? Stefan -- You received this message because you are

[linux-sunxi] Re: [PATCH 5/7] mtd: provide helper to prepare buffers for DMA operations

On Tue, Mar 08, 2016 at 12:15:13PM +0100, Boris Brezillon wrote: > > +#ifdef CONFIG_HAS_DMA Shouldn't this be CONFIG_DMA_ENGINE as you are preparing these descriptors for DMA transfer? -- ~Vinod -- You received this message because you are subscribed to the Google Groups "linux-sunxi"

[linux-sunxi] [PATCH 0/7] mtd: nand: sunxi: add support for DMA operations

Hello, This patch series aims at adding support for DMA assisted operations to the sunxi_nand driver. The first 3 patches are just reworks in the existing driver preparing things for DMA ->read/write_page() operations. Those ones are mainly re-arranging existing functions, and moving some code

[linux-sunxi] [PATCH 4/7] scatterlist: add sg_alloc_table_from_buf() helper

sg_alloc_table_from_buf() provides an easy solution to create an sg_table from a virtual address pointer. This function takes care of dealing with vmallocated buffers, buffer alignment, or DMA engine limitations (maximum DMA transfer size). Signed-off-by: Boris Brezillon

[linux-sunxi] [PATCH 7/7] mtd: nand: sunxi: update DT bindings

Document dmas and dma-names properties. Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/sunxi-nand.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt

[linux-sunxi] [PATCH 3/7] mtd: nand: sunxi: make cur_off parameter optional in extra oob helpers

Allow for NULL cur_offs values when the caller does not know where the NAND page register pointer point to. Signed-off-by: Boris Brezillon --- drivers/mtd/nand/sunxi_nand.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git

[linux-sunxi] [PATCH 6/7] mtd: nand: sunxi: add support for DMA assisted operations

The sunxi NAND controller is able to pipeline ECC operations only when operated in DMA mode, which improves a lot NAND throughput while keeping CPU usage low. Signed-off-by: Boris Brezillon --- drivers/mtd/nand/sunxi_nand.c | 301

[linux-sunxi] [PATCH 5/7] mtd: provide helper to prepare buffers for DMA operations

Some NAND controller drivers are making use of DMA to transfer data from the controller to the buffer passed by the MTD user. Provide a generic mtd_map/unmap_buf() implementation to avoid open coded (and sometime erroneous) implementations. Signed-off-by: Boris Brezillon

[linux-sunxi] [PATCH 2/7] mtd: nand: sunxi: make OOB retrieval optional

sunxi_nfc_hw_ecc_read_chunk() always retrieves the ECC and protected free bytes, no matter if the user really asked for it or not. This can take a non negligible amount of time, especially on NAND chips exposing large OOB areas (> 1KB). Make it optional. Signed-off-by: Boris Brezillon

Re: [linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

On Tue, Mar 08, 2016 at 09:42:31AM +0100, Hans de Goede wrote: > > > I see 2 possible reasons why waiting till checking for drq can help: > > 1) A lot of devices have an internal fifo hooked up to a single mmio data > register which gets read using the general purpose dma-engine, it allows >

[linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

On Tue, Mar 08, 2016 at 09:46:25AM +0100, Boris Brezillon wrote: > On Tue, 8 Mar 2016 08:51:31 +0100 > Maxime Ripard wrote: > > > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote: > > > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote: > >

[linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

On Tue, Mar 08, 2016 at 08:51:31AM +0100, Maxime Ripard wrote: > > > > > > + * struct sun4i_dma_chan_config - DMA channel config > > > > > > + * > > > > > > + * @para: contains information about block size and time before > > > > > > checking > > > > > > + * DRQ line. This is device specific

[linux-sunxi] [PATCH v4] drivers: pinctrl: add driver for Allwinner A64 SoC

Based on the Allwinner A64 user manual and on the previous sunxi pinctrl drivers this introduces the pin multiplex assignments for the ARMv8 Allwinner A64 SoC. Port A is apparently used for the fixed function DRAM controller, so the ports start at B here (the manual mentions "n from 1 to 7", so

Re: [linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

On Tue, 2016-03-08 at 09:46 +0100, Boris Brezillon wrote: > On Tue, 8 Mar 2016 08:51:31 +0100 > Maxime Ripard wrote: > > > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote: > > > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote: > > > > On

[linux-sunxi] Re: [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins

On Mon, Feb 29, 2016 at 6:13 AM, Henry Paulissen wrote: > While I was testing irq's on the cubietruck I found a couple of > not working irq pins. Further diving into the problem it opened > up a mess called "manual". > > This so called manual (A20 user manual v1.3 dated

[linux-sunxi] Re: [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's

On Mon, Feb 29, 2016 at 6:13 AM, Henry Paulissen wrote: > While I was testing irq's on the cubietruck I found a couple of > not working irq pins. Further diving into the problem it opened > up a mess called "manual". > > This so called manual (A20 user manual v1.3 dated

[linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

On Tue, 8 Mar 2016 08:51:31 +0100 Maxime Ripard wrote: > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote: > > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote: > > > On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote: > > > >

Re: [linux-sunxi] Re: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

Hi, On 08-03-16 08:51, Maxime Ripard wrote: On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote: On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote: On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote: Hi Vinod, On Mon, 7 Mar 2016 20:24:29 +0530 Vinod Koul