On Thu, Mar 24, 2016 at 12:38 AM, Maxime Ripard
wrote:
> The DRAM gates control whether the image / display devices on the SoC have
> access to the DRAM clock or not.
>
> Enable it.
>
> Signed-off-by: Maxime Ripard
Acked-by:
The Orange Pi Plus really is an Orange Pi 2 extended with:
1) A sata <-> usb bridge connected to ehci3
2) An eMMC on mmc2
3) An external gigabit ethernet phy instead of the integrated 100Mbit phy
This commit changes the dts to reflect this by making it include
the Orange Pi 2 dts and then adding
The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.
Enable it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 22 +-
arch/arm/boot/dts/sun5i-r8.dtsi | 2 +-
2
Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.
Add support for that TV encoder.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile |
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard
Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 42
1
Add the settings to support the NTSC standard.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c
The CHIP has a composite output available muxed with the microphone in the
micro-jack plug.
Enable the composite output in its DTS.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 12
1 file changed, 12 insertions(+)
diff
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.
Add a driver to support both.
Signed-off-by: Maxime Ripard
Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i.dtsi | 43 +++
1 file changed,
Hi everyone,
The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.
Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.
Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it
Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 38
Otherwise, building with DEBUG_FS enabled will trigger a build warning
because we're using a structure that has not been declared.
Signed-off-by: Maxime Ripard
---
include/drm/drm_fb_cma_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.
While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.
Add a
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.
Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually
Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.
It is a 480x272 panel connected through a 24-bits RGB interface.
Signed-off-by: Maxime Ripard
Acked-by: Rob Herring
---
One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile
The display pipeline of the Allwinner A10 is involving several loosely
coupled components.
Add a documentation for the bindings.
Signed-off-by: Maxime Ripard
---
.../bindings/display/sunxi/sun4i-drm.txt | 254 +
1 file changed,
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
Signed-off-by:
instead of memset() and strcpy() to clear / assign member fields.
Signed-off-by: Bernhard Nortmann
---
fel.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/fel.c b/fel.c
index 495aa81..62f2fa8 100644
--- a/fel.c
+++
- Do a clean shutdown / exit(0) after printing usage help,
instead of continuing execution. This avoids the "ERROR:
Allwinner USB FEL device not found!" when doing a plain
./sunxi-fel without any arguments.
- Convert C++ style comments for a uniform coding style.
- Some small formatting
Signed-off-by: Bernhard Nortmann
---
fel.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/fel.c b/fel.c
index 0a36607..495aa81 100644
--- a/fel.c
+++ b/fel.c
@@ -322,16 +322,14 @@ void hexdump(void *data, uint32_t offset, size_t size)
Changes in v2:
- Rebased to current master
- Added some formatting adjustments
- Added a second patch that simplifies hexdump()
Changes in v3:
- Convert "needs_l2en" to boolean type.
- Add another patch that uses initializers for aw_(usb|fel)_request
Bernhard Nortmann (3):
fel: Minor fixes
Hello Siarhei!
I'm still catching up in my understanding of the concepts and inner
workings of the fel utility and its relationship with the BROM code.
Thanks to your detailed explanations, the picture has gotten a lot clearer.
What's the expected usage (required size in bytes) of the
On Mon, Mar 21, 2016 at 3:52 PM, Maxime Ripard
wrote:
> On Sat, Mar 19, 2016 at 11:18:59PM +0800, Chen-Yu Tsai wrote:
>> On Sat, Mar 19, 2016 at 3:53 PM, Hans de Goede wrote:
>> > The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips
On Tue, Mar 22, 2016 at 4:01 AM, wrote:
> From: Marcus Cooper
nit: space should be after colon, not after dts, in subject.
Same for the RX pin patch.
ChenYu
> Add the SPDIF TX pin to the A20 dtsi.
>
> Signed-off-by: Marcus Cooper
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot,
4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI,
a TRRS headphone jack for stereo out and composite out, a microphone,
an IR
28 matches
Mail list logo