[linux-sunxi] [PATCH v2 1/1] add missing UARTs pins and I2C entriesfor AllWinner H3 DTSI

Hi everyone, This patch is submit to provide endusers access to additional UARTs on AllWinner H3 SoC along with I2C ports. Regards, Martin. --- arch/arm/boot/dts/sun8i-h3.dtsi | 75 + 1 file changed, 75 insertions(+) diff --git

Re: [linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

On 19 April 2016 at 17:11, Chen-Yu Tsai wrote: > On Tue, Apr 19, 2016 at 10:46 PM, wrote: >> Hi ChenYu, >> >> Thanks for your comments. >> >> On Tuesday, April 19, 2016 at 7:11:50 AM UTC-4, Chen-Yu Tsai wrote: >>> Hi, >>> >>> >

[linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

Oupps ! sorry for again have a line length exceeding 80 chars. Regards, -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to

[linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

On Tuesday, April 19, 2016 at 11:11:37 AM UTC-4, Chen-Yu Tsai wrote: > Try to wrap lines to 80 characters or less. Ok ! I will be more careful ... > 1 change per patch. You are making 3 changes here. a) adding shared > pinmux settings, > b & c) enabling uarts and i2c busses for 2 boards. > >

[linux-sunxi] [PATCH v2] sunxi factors clock predivider handling

For allwinner A31 ahb1 and a83t ahb1 clocks have predivider for certain parent. Currently, it's being handled in clock specific functions. A83t ahb1 and a31 ahb1 are similar clocks except a83t parent index 0b10 and 0b11 are pll6/prediv and a31 ahb1 parent index 0x11 is pll6/prediv. with only

[linux-sunxi] [PATCH v2] clk: sunxi: predivider handling for factors clock

For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent. To handle this, this patch adds predivider table with parent index, prediv shift and width, parents with predivider will have nonzero width. Rate adjustment is moved from clock specific recalc function to generic factors

[linux-sunxi] Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

Hello Wens, On Tue, Apr 19, 2016 at 10:16 PM, Chen-Yu Tsai wrote: > On Tue, Apr 19, 2016 at 6:22 PM, Philip Li wrote: >> On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote: >>> Both of these patches in series has to be applied at the same time.

[linux-sunxi] Re: random decryption errors with sun4i-ss on dm-crypt

Still nothing :( it seems i can convert my encrypted storage back to XTS, as i've only converted it to CBC for the hw encryption. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it,

[linux-sunxi] Re: [PATCH v4 0/3] dmaengine: sun6i: Upgrade for audio transfers

On Sat, Apr 02, 2016 at 11:49:13AM +0200, Jean-Francois Moine wrote: > This patch series contains most of the required changes to > the sun6i DMA driver for audio streaming (tested in > a Allwinner H3 - Orange PI 2). > It is based on the previous series 'dmaengine: sun6i: Fixes' > (2016-03-18).

[linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

On Tue, Apr 19, 2016 at 10:46 PM, wrote: > Hi ChenYu, > > Thanks for your comments. > > On Tuesday, April 19, 2016 at 7:11:50 AM UTC-4, Chen-Yu Tsai wrote: >> Hi, >> >> > arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 36 ++ >> >

[linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

Hi ChenYu, Thanks for your comments. On Tuesday, April 19, 2016 at 7:11:50 AM UTC-4, Chen-Yu Tsai wrote: > Hi, > > > arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 36 ++ > > arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 36 ++ > > arch/arm/boot/dts/sun8i-h3.dtsi

[linux-sunxi] Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

On Tue, Apr 19, 2016 at 6:22 PM, Philip Li wrote: > On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote: >> Both of these patches in series has to be applied at the same time. >> I think this is the reason, it fails. You should probably squash the second patch

[linux-sunxi] Re: [PATCH v5 39/50] mtd: nand: omap2: switch to mtd_ooblayout_ops

On 19/04/16 15:41, Boris Brezillon wrote: > On Tue, 19 Apr 2016 15:30:39 +0300 > Roger Quadros wrote: > >> On 19/04/16 14:22, Boris Brezillon wrote: >>> Hi Roger, >>> >>> On Tue, 19 Apr 2016 13:28:50 +0300 >>> Roger Quadros wrote: >>> > @@ -1921,6 +1927,9 @@

[linux-sunxi] Re: [PATCH v5 39/50] mtd: nand: omap2: switch to mtd_ooblayout_ops

On Tue, 19 Apr 2016 15:30:39 +0300 Roger Quadros wrote: > On 19/04/16 14:22, Boris Brezillon wrote: > > Hi Roger, > > > > On Tue, 19 Apr 2016 13:28:50 +0300 > > Roger Quadros wrote: > > > >>> @@ -1921,6 +1927,9 @@ static int omap_nand_probe(struct platform_device

[linux-sunxi] Re: [PATCH v5 39/50] mtd: nand: omap2: switch to mtd_ooblayout_ops

On 19/04/16 14:22, Boris Brezillon wrote: > Hi Roger, > > On Tue, 19 Apr 2016 13:28:50 +0300 > Roger Quadros wrote: > >>> @@ -1921,6 +1927,9 @@ static int omap_nand_probe(struct platform_device >>> *pdev) >>> nand_chip->ecc.correct = omap_correct_data; >>>

[linux-sunxi] Re: [PATCH v5 39/50] mtd: nand: omap2: switch to mtd_ooblayout_ops

Hi Roger, On Tue, 19 Apr 2016 13:28:50 +0300 Roger Quadros wrote: > > @@ -1921,6 +1927,9 @@ static int omap_nand_probe(struct platform_device > > *pdev) > > nand_chip->ecc.correct = omap_correct_data; > > mtd_set_ooblayout(mtd, _ooblayout_ops); >

[linux-sunxi] Re: [PATCH v1 1/1] add missing UARTs pins for AllWinner H3 DTS + add new I2C entries for AllWinner H3 DTS

Hi, On Sat, Apr 16, 2016 at 1:11 AM, Martin Ayotte wrote: > Hi everyone, > > This patch is submit to provide endusers access to additional UARTs on > AllWinner H3 SoC along with I2C ports. > > Regards, > Martin. > --- > arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 36

[linux-sunxi] Re: [PATCH v5 39/50] mtd: nand: omap2: switch to mtd_ooblayout_ops

On 18/04/16 18:05, Boris Brezillon wrote: > On Mon, 18 Apr 2016 17:32:49 +0300 > Roger Quadros wrote: > >> Boris, >> >> On 30/03/16 19:14, Boris Brezillon wrote: >>> Implementing the mtd_ooblayout_ops interface is the new way of exposing >>> ECC/OOB layout to MTD users. >>> >>>

[linux-sunxi] Re: [PATCH 1/2] clk: sunxi: add predivider handling for factors clock

On Sun, Apr 17, 2016 at 11:53:47AM +0800, Vishnu Patekar wrote: > Both of these patches in series has to be applied at the same time. > I think this is the reason, it fails. hi Xiaolong, would you help do a check whether we apply the patches in correct sequence for this case? > On 17 Apr 2016

[linux-sunxi] Re: [PATCH v3 08/19] ARM: sun5i: Add DRAM gates

On Wed, Mar 23, 2016 at 05:38:31PM +0100, Maxime Ripard wrote: > The DRAM gates control whether the image / display devices on the SoC have > access to the DRAM clock or not. > > Enable it. > > Signed-off-by: Maxime Ripard Applied, Maxime -- Maxime Ripard,

[linux-sunxi] Re: [PATCH v3 09/19] ARM: sun5i: Add TV encoder gate to the DTSI

On Wed, Mar 23, 2016 at 05:38:32PM +0100, Maxime Ripard wrote: > It turns out that the A13 / R8 also have a tve encoder block, and a gate > for it. > > Add it to the DT. > > Signed-off-by: Maxime Ripard > Acked-by: Chen-Yu Tsai Applied, Maxime

[linux-sunxi] Re: [PATCH v3 06/19] ARM: sun5i: dt: Add pll3 and pll7 clocks

On Wed, Mar 23, 2016 at 05:38:29PM +0100, Maxime Ripard wrote: > Enable the pll3 and pll7 clocks in the DT that are used to drive the > display-related clocks. > > Signed-off-by: Maxime Ripard > Acked-by: Chen-Yu Tsai Applied, Maxime --

[linux-sunxi] Re: [PATCH v3 01/19] clk: composite: Add unregister function

Hi, On Fri, Apr 15, 2016 at 03:28:56PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The composite clock didn't have any unregistration function, which forced > > us to use clk_unregister directly on it. > > > > While it was already not great from an API point of view, it also

[linux-sunxi] Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > > > >

[linux-sunxi] Re: [PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible

On Fri, Apr 15, 2016 at 03:29:11PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The Allwinner SoCs have a gate controller to gate the access to the DRAM > > clock to the some devices that need to access the DRAM directly (mostly > > display / image related IPs). > > > > Use a