Hello Tom, Boris,
Am 25.04.2016 um 19:36 schrieb Tom Rini:
On Mon, Apr 25, 2016 at 04:43:14PM +0200, Boris Brezillon wrote:
Hi Scott,
I've recently contributed a lot of MTD/NAND related patches (and intend
to continue doing so). Some of them are transversal changes touching the
MTD and NAND
On Fri, Apr 22, 2016 at 08:47:29AM +0200, Jean-Francois Moine wrote:
> Checking the DMA config before setting the lli list avoids to do tests
> inside the setting loop.
Applied, thanks
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On Fri, Apr 22, 2016 at 08:49:55AM +0200, Jean-Francois Moine wrote:
> DMA cyclic transfers are required by audio streaming.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Jean-Francois Moine
> ---
> drivers/dma/sun6i-dma.c | 129
>
On Fri, Apr 22, 2016 at 08:48:40AM +0200, Jean-Francois Moine wrote:
> Some DMA clients, as audio, don't set the maxburst size and bus width
> on the memory side when starting DMA transfers.
> This patch prevents such transfers to be aborted by providing system
> default values to the lacking
On Fri, Apr 22, 2016 at 08:22:56AM +0200, Jean-Francois Moine wrote:
> This patch series replaces part of the previous series
> 'dmaengine: sun6i: Fixes and upgrade for audio transfers'.
> It contains only fixes for a normal use of the DMA driver.
Applied, thanks
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On Mon, 25 Apr 2016 13:36:46 -0400
Tom Rini wrote:
> On Mon, Apr 25, 2016 at 04:43:14PM +0200, Boris Brezillon wrote:
>
> > Hi Scott,
> >
> > I've recently contributed a lot of MTD/NAND related patches (and intend
> > to continue doing so). Some of them are transversal
Hi Maxime,
On 25 April 2016 at 14:22, Maxime Ripard
wrote:
> Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
> .../bindings/display/sunxi/sun4i-drm.txt | 258
> arch/arm/boot/dts/sun5i-a13.dtsi | 39 +-
>
On Mon, Apr 25, 2016 at 04:43:14PM +0200, Boris Brezillon wrote:
> Hi Scott,
>
> I've recently contributed a lot of MTD/NAND related patches (and intend
> to continue doing so). Some of them are transversal changes touching the
> MTD and NAND framework internals, which implies patching all NAND
On Tue, 29 Mar 2016, Chen-Yu Tsai wrote:
> Add an entry for X-Powers AXP family PMIC drivers and list myself
> as maintainer.
>
> Cc: Carlo Caione
> Cc: Maxime Ripard
> Cc: Ramakrishna Pallala
> Cc: Todd Brandt
Hi,
On Wed, Apr 20, 2016 at 12:47 AM, Vishnu Patekar
wrote:
> For A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.
> To handle this, this patch adds predivider table with parent index,
> prediv shift and width, parents with predivider will have
Hi Scott,
I've recently contributed a lot of MTD/NAND related patches (and intend
to continue doing so). Some of them are transversal changes touching the
MTD and NAND framework internals, which implies patching all NAND
drivers along with the core changes.
All those changes are required to
On Monday, April 25, 2016 at 2:23:42 PM UTC+2, Irvin Probst wrote:
>
> Thanks I know these pages but I'm fighting with dts/dtb, not fex/bin...
> Maybe what I'm asking is obvious but I'm really lost.
>
OK I got it, for the record if anybody has the same problem in the future
the right entry point
Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 42
1
Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.
Add support for that TV encoder.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile |
The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.
Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it
The CHIP has a composite output available muxed with the microphone in the
micro-jack plug.
Enable the composite output in its DTS.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 12
1 file changed, 12 insertions(+)
diff
Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 39
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.
Add a driver to support both.
Signed-off-by: Maxime Ripard
Add the settings to support the NTSC standard.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c
Hi everyone,
The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.
Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile
The display pipeline of the Allwinner A10 is involving several loosely
coupled components.
Add a documentation for the bindings.
Signed-off-by: Maxime Ripard
---
.../bindings/display/sunxi/sun4i-drm.txt | 258 +
1 file changed,
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.
Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually
Otherwise, building with DEBUG_FS enabled will trigger a build warning
because we're using a structure that has not been declared.
Signed-off-by: Maxime Ripard
---
include/drm/drm_fb_cma_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
>
> Please use (and improve) our Wiki:
>
> https://linux-sunxi.org/GPIO
> https://linux-sunxi.org/LinkSprite_pcDuino3
>
>
>
Thanks I know these pages but I'm fighting with dts/dtb, not fex/bin...
Maybe what I'm asking is obvious but I'm really lost.
Thanks
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On Mon, 2016-04-25 at 04:12 -0700, Irvin Probst wrote:
> Hi,
> I'm trying to upgrade a pcduino 3 to the 4.4.x kernel branch and
> configure it as it was by default when unboxing.
>
> The easy part was to re-enable i2c-1 and i2c-2 and modify the
> section to have the ethernet port again. However
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