On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
>
> 2017年2月13日 15:17于 Maxime Ripard 写道:
> >
> > Hi,
> >
> > On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote:
> > > @@ -0,0 +1,13 @@
> > > +CONFIG_ARM=y
> > > +CONFIG_ARCH_SUNXI=y
>
On Tue, Feb 14, 2017 at 5:41 AM, Bob Ham wrote:
> On Mon, 2017-02-13 at 10:52 +0100, Maxime Ripard wrote:
>> On Sat, Feb 11, 2017 at 12:08:40PM +, Bob Ham wrote:
>> > On IRC, MoeIcenowy requested the contents
>> > of /sys/kernel/debug/clk/clk_summary. I don't know how
On Mon, 2017-02-13 at 10:52 +0100, Maxime Ripard wrote:
> On Sat, Feb 11, 2017 at 12:08:40PM +, Bob Ham wrote:
> > On IRC, MoeIcenowy requested the contents
> > of /sys/kernel/debug/clk/clk_summary. I don't know how useful it will
> > be but I've put up two versions, one from the bad commit
On Mon, Feb 13, 2017 at 04:00:09PM -0300, Vinicius Maciel wrote:
> Hi Mark,
Please don't top post, reply in line with needed context. This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion
Hi Mark,
Sorry for the mess up. sun6i is a reference to the Allwinner A31 processor
and sun7i is a reference to the Allwinner A20 processor. A31 uses
spi-sun6i.c code, while A20 uses spi-sun4i.c code. Therefore, this is a
different patch.
About your recommedantion, I have to check with Maxine
2017年2月13日 23:09于 Chen-Yu Tsai 写道:
>
> On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng wrote:
> > The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> > Add support for the pins controlled by the R_PIO controller.
> >
> > Signed-off-by:
On Mon, 2017-02-13 at 17:20 +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 13, 2017 at 5:16 PM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Sat, Feb 11, 2017 at 07:43:59PM +0200, Priit Laes wrote:
> > > Added basic display pipeline consisting of tcon, display backend
>
On Sun, 2017-02-12 at 23:22 -0800, Philippe Fouquet wrote:
> No, I try the branches sun4i-lvds-wip sun4i-lvds-v1 all have the same
> results.
>
> they have some diff?
The sun4i-lvds-wip branch I have in the repository is currently broken
- mainly an experiment to add the LVDS reset line handling
On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On Wed, Feb 8, 2017 at 6:00 PM, Icenowy Zheng wrote:
> The compatible for Allwinner H5 pin controller is wrong written as
> allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
> rather than a "r" one.
>
> Fix this compatible string.
>
> Signed-off-by: Icenowy
On Wed, Feb 8, 2017 at 11:00 AM, Icenowy Zheng wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
>
> Signed-off-by: Icenowy Zheng
I'd be happy to merge patches
On Sat, Feb 11, 2017 at 12:54:47AM -0300, Vinicius Maciel wrote:
> In order to work appropriately, the max11043 ADC chip and probably
> others, needs SPI master samples the data at the correct edge. From
> max11043 datasheet: "The data at DIN is latched on the rising edge
> of SCLK". Same to DOUT.
In order to work appropriately, some SPI chips, such as
max11043, require SPI master samples the data at the
correct edge.
This patch add Master Sample Data Mode bit in normal sample mode.
Signed-off-by: Vinicius Maciel
---
drivers/spi/spi-sun6i.c | 3 +++
1 file
Hi,
On Sat, Feb 11, 2017 at 12:08:40PM +, Bob Ham wrote:
> Hi there,
>
> I have a Mele A1000G Quad top set box with an Allwinner A31 chip.
> Unfortunately, the framebuffer is failing on recent kernels. I have a
> 1080p monitor connected to the HDMI output. During boot, the monitor
> goes
Hi,
On Sat, Feb 11, 2017 at 07:43:59PM +0200, Priit Laes wrote:
> Added basic display pipeline consisting of tcon, display backend and
> frontend blocks.
>
> Signed-off-by: Priit Laes
> ---
> arch/arm/boot/dts/sun4i-a10.dtsi | 104
> +++
>
On Sat, Feb 11, 2017 at 07:44:02PM +0200, Priit Laes wrote:
> Depending on the output type, we have to enable/disable some
> bits conditionally.
>
> Signed-off-by: Priit Laes
> ---
> drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 +-
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 3 ++-
>
Hi,
On Sat, Feb 11, 2017 at 07:44:01PM +0200, Priit Laes wrote:
> Add variable to enable either 'rgb' or 'lvds' output.
>
> Signed-off-by: Priit Laes
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
On Sat, Feb 11, 2017 at 07:44:04PM +0200, Priit Laes wrote:
> TODO: We still rely on u-boot for lvds reset bit setup :(
That needs to be figured out before merging :/
You also have a number of checkpatch warnings / errors that needs to
be fixed.
>
> Signed-off-by: Priit Laes
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