Hi Icenowy,
(Please fix your mailer, its quotation is broken and mangles all the
indentation)
On Thu, Feb 23, 2017 at 04:28:42AM +0800, Icenowy Zheng wrote:
> >> @@ -187,3 +220,30 @@ struct sun4i_layer **sun4i_layers_init(struct
> >> drm_device *drm)
> >>
> >> return layers;
> >> }
Hi,
Dne sreda, 22. februar 2017 ob 21:17:29 CET je Icenowy Zheng napisal(a):
> 2017年2月23日 03:09于 Maxime Ripard 写道：
>
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> > > +config SUNXI_DE2_CCU
> > > + bool "Support for the Allwinner SoCs DE2 CCU"
> > > + select SUN
Hi,
Dne sreda, 22. februar 2017 ob 16:18:50 CET je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
> in a new "Display Engine" (mixers instead of old backends and
> frontends).
>
> Add support for the mixer on Allwinner V3s SoC; it's the simple
23.02.2017, 06:01, "Jernej Škrabec" :
> Hi,
>
> Dne sreda, 22. februar 2017 ob 16:18:50 CET je Icenowy Zheng napisal(a):
>> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
>> in a new "Display Engine" (mixers instead of old backends and
>> frontends).
>>
>> Add suppor
23.02.2017, 04:09, "Maxime Ripard" :
> Hi,
>
> On Wed, Feb 22, 2017 at 11:23:06PM +0800, Icenowy Zheng wrote:
>> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
>> in a new "Display Engine" (mixers instead of old backends and
>> frontends).
>>
>> Add support for the m
2017年2月23日 03:09于 Maxime Ripard 写道：
>
> Hi,
>
> On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> > +config SUNXI_DE2_CCU
> > + bool "Support for the Allwinner SoCs DE2 CCU"
> > + select SUNXI_CCU_DIV
> > + select SUNXI_CCU_GATE
> > + default n
>
> This is already the default
2017年2月22日 07:03于 Maxime Ripard 写道：
>
> Hi,
>
> On Sat, Feb 18, 2017 at 01:37:17AM +0800, Icenowy Zheng wrote:
> > Allwinner R40 SoC have a clock controller module in the style of the
> > SoCs beyond sun6i, however, it's more rich and complex.
> >
> > Add support for it.
> >
> > As the user
Hi,
On Wed, Feb 22, 2017 at 11:23:06PM +0800, Icenowy Zheng wrote:
> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
> in a new "Display Engine" (mixers instead of old backends and
> frontends).
>
> Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
>
Hi,
On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> +config SUNXI_DE2_CCU
> + bool "Support for the Allwinner SoCs DE2 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_GATE
> + default n
This is already the default.
> +
> endif
> diff --git a/drivers/clk/sunxi
If an SoC has the "secure boot" fuse burned, it will enter FEL mode in
non-secure state, so with the SCR.NS bit set. Since in this mode the
secure/non-secure state restrictions are actually observed, we suffer
from several restrictions:
- No access to the SID information (both via memory mapped and
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 87
1 file changed, 87 insertions(+)
diff --
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/
Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
in a new "Display Engine" (mixers instead of old backends and
frontends).
Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/Kconfig | 8 +
Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
in a new "Display Engine" (mixers instead of old backends and
frontends).
Add support for the mixer on Allwinner V3s SoC; it's the simplest one.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/Kconfig | 8 +
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
The paragraph of TCON is also refactored, for furtherly add TCONs in
A83T/H3/A64/H5 that have only a channel 1 (used for HDMI or TV Encoder).
S
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 6 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/
Allwinner "Display Engine 2.0" contains some clock controls in it.
Add them as a clock driver.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-de2.txt| 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/
This patchset is the initial patchset for Allwinner DE2 support.
It contains the support of clocks in DE2 and the mixers in DE2.
The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs that have DE2.
(Allwinner V3s features only one mixer, although its clock control
u
07.12.2016, 05:03, "Maxime Ripard" :
> On Thu, Nov 24, 2016 at 07:22:31PM +0800, Chen-Yu Tsai wrote:
>> The panels shipped with Allwinner devices are very "generic", i.e.
>> they do not have model numbers or reliable sources of information
>> for the timings (that we know of) other than the fe
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