在 2017-06-07 22:38，Maxime Ripard 写道：
On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
>I have no idea what this is supposed to be doing either.
>
>I might be wrong, but I really feel like there's a big mismatch
>between your commit log, and what you actually implement.
>
>In your c
On Fri, Jun 02, 2017 at 06:10:11PM +0800, Chen-Yu Tsai wrote:
> The HDMI controller in the A31 SoC is slightly different from the
> earlier version. In addition to the TMDS clock and DDC controls,
> this version now takes a second DDC clock input.
>
> Add a compatible string for it, and add the DD
On Fri, Jun 02, 2017 at 09:42:19PM +0200, Maxime Ripard wrote:
> On Fri, Jun 02, 2017 at 06:10:24PM +0800, Chen-Yu Tsai wrote:
> > The MSI Primo81 tablet has a micro HDMI connector at the bottom.
> > This is connected to the SoCs HDMI output.
> >
> > Enable the display pipeline and the HDMI output
On Wed, May 31, 2017 at 03:58:19PM +0800, Chen-Yu Tsai wrote:
> The AR100 clock in the PRCM has parents, one of which is pll-periph from
> the main CCU.
>
> Add it to the list of required clocks for the PRCM CCU.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> Documentation/devicetree/bindings/clock/su
Hi!
Dne sreda, 07. junij 2017 ob 16:38:27 CEST je Maxime Ripard napisal(a):
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is supposed to be doing either.
> > >
> > >I might be wrong, but I really feel like there's a big mismatch
> > >between your co
On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> >I have no idea what this is supposed to be doing either.
> >
> >I might be wrong, but I really feel like there's a big mismatch
> >between your commit log, and what you actually implement.
> >
> >In your commit log, you should state:
于 2017年6月7日 GMT+08:00 下午10:19:57, Maxime Ripard
写到:
>On Wed, Jun 07, 2017 at 05:44:56PM +0800, Icenowy Zheng wrote:
>> 于 2017年6月7日 GMT+08:00 下午5:43:43, Maxime Ripard
> 写到:
>> >On Mon, Jun 05, 2017 at 03:03:47AM +0800, Icenowy Zheng wrote:
>> >> >You should also expand function sun4i_drv_node_is
On Wed, Jun 07, 2017 at 05:44:56PM +0800, Icenowy Zheng wrote:
> 于 2017年6月7日 GMT+08:00 下午5:43:43, Maxime Ripard
> 写到:
> >On Mon, Jun 05, 2017 at 03:03:47AM +0800, Icenowy Zheng wrote:
> >> >You should also expand function sun4i_drv_node_is_tcon() at
> >sun4i_drv.c
> >> >with
> >> >new entries, b
On 07/06/17 14:04, Maxime Ripard wrote:
> On Wed, Jun 07, 2017 at 01:51:48PM +0100, Marc Zyngier wrote:
>> On 07/06/17 13:12, Icenowy Zheng wrote:
>>>
>>>
>>> 于 2017年6月7日 GMT+08:00 下午8:11:12, Marc Zyngier 写到:
On 07/06/17 08:00, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at 2:50 PM, Maxime
It depends on what are your requirements, i tested analogue CVBS and it
works ok with 4 channels simultaneous..
You can combine how do you want this tv inputs.. tvin0..4
I also tested long time ago CSI digital port with ov7670 but i do not
remember which one CSI0 or CSI1.. And i think that i had
On Wed, Jun 07, 2017 at 08:23:05AM +0800, Icenowy Zheng wrote:
> Add the required DT parts to enable Ethernet (dwmac-sun8i driver) on
> the Nano Pi NEO2 board. It uses an external Realtek RTL8211E PHY
> connected via RGMII to provide GbE network. Specially unlike other
> Allwinner boards, the phy i
On Wed, Jun 07, 2017 at 01:51:48PM +0100, Marc Zyngier wrote:
> On 07/06/17 13:12, Icenowy Zheng wrote:
> >
> >
> > 于 2017年6月7日 GMT+08:00 下午8:11:12, Marc Zyngier 写到:
> >> On 07/06/17 08:00, Chen-Yu Tsai wrote:
> >>> On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
> >>> wrote:
> On Wed, Jun 0
On 07/06/17 13:12, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 下午8:11:12, Marc Zyngier 写到:
>> On 07/06/17 08:00, Chen-Yu Tsai wrote:
>>> On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
>>> wrote:
On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at
于 2017年6月7日 GMT+08:00 下午5:35:12, Maxime Ripard
写到:
>On Mon, Jun 05, 2017 at 12:01:41AM +0800, Icenowy Zheng wrote:
>> Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
>> tcon0 and mixer1 is connected to tcon1; however by setting a bit
>> the connection can be swapped.
>>
>>
于 2017年6月7日 GMT+08:00 下午5:43:43, Maxime Ripard
写到:
>On Mon, Jun 05, 2017 at 03:03:47AM +0800, Icenowy Zheng wrote:
>> >You should also expand function sun4i_drv_node_is_tcon() at
>sun4i_drv.c
>> >with
>> >new entries, but I'm not sure if this fits in this patch.
>>
>> Instead I think it shoul
于 2017年6月7日 GMT+08:00 下午8:11:12, Marc Zyngier 写到:
>On 07/06/17 08:00, Chen-Yu Tsai wrote:
>> On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
>> wrote:
>>> On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng
>wrote:
>
>
> 于
On 07/06/17 08:00, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
> wrote:
>> On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
>>> On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
> On We
于 2017年6月7日 GMT+08:00 下午5:43:43, Maxime Ripard
写到:
>On Mon, Jun 05, 2017 at 03:03:47AM +0800, Icenowy Zheng wrote:
>> >You should also expand function sun4i_drv_node_is_tcon() at
>sun4i_drv.c
>> >with
>> >new entries, but I'm not sure if this fits in this patch.
>>
>> Instead I think it shoul
于 2017年6月7日 GMT+08:00 下午5:35:12, Maxime Ripard
写到:
>On Mon, Jun 05, 2017 at 12:01:41AM +0800, Icenowy Zheng wrote:
>> Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
>> tcon0 and mixer1 is connected to tcon1; however by setting a bit
>> the connection can be swapped.
>>
>>
On Mon, Jun 05, 2017 at 03:03:47AM +0800, Icenowy Zheng wrote:
> >You should also expand function sun4i_drv_node_is_tcon() at sun4i_drv.c
> >with
> >new entries, but I'm not sure if this fits in this patch.
>
> Instead I think it should be renamed to something like
> "sun4i_drv_node_is_tcon_with_
Hello,
Is it possible to flash nand from linux command line?
I tried Phoenixsuite, PhoenixUSBPro and Livesuite on Win7, livesuit for
linux but it is also graphical..
Thanks,
Milos
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On Mon, Jun 05, 2017 at 12:01:48AM +0800, Icenowy Zheng wrote:
> + soc {
> + display_clocks: clock@100 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x0100 0x10>;
> + clocks = <&ccu CLK_BUS_DE>,
On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
> but has a internal fixed clock divider that divides the TCON1 clock
> (called TVE clock in datasheet) by 11.
>
> Add support for it.
>
> Signed-off-by: Icenowy
On Mon, Jun 05, 2017 at 12:01:41AM +0800, Icenowy Zheng wrote:
> Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
> tcon0 and mixer1 is connected to tcon1; however by setting a bit
> the connection can be swapped.
>
> As we now hardcode the default connection, ignore the bonus e
于 2017年6月7日 GMT+08:00 下午4:45:44, Maxime Ripard
写到:
>On Mon, Jun 05, 2017 at 12:01:39AM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a "DE2.0" and a TV Encoder.
>>
>> Add device tree bindings for the following parts:
>> - H3 TCONs
>> - H3 Mixers
>> - The connection between H3 TCONs and
On Mon, Jun 05, 2017 at 12:01:39AM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a "DE2.0" and a TV Encoder.
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - The connection between H3 TCONs and H3 Mixers
> - H3 TV Encoder
> - H3 Display engine
>
> Signed-
On Sun, Jun 04, 2017 at 10:29:29PM +0800, icen...@aosc.io wrote:
> 在 2017-05-24 15:30，Maxime Ripard 写道：
> > On Tue, May 23, 2017 at 09:00:59PM +0800, icen...@aosc.io wrote:
> > > 在 2017-05-23 20:53，Maxime Ripard 写道：
> > > > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej Škrabec wrote:
> > > > > H
On 07/06/17 07:59, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 下午2:48:55, Maxime Ripard
> 写到:
>> Hi,
>>
>> On Wed, Jun 07, 2017 at 08:47:20AM +0800, Icenowy Zheng wrote:
>>> From: Chen-Yu Tsai
>>>
>>> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
>>> contains 4 cores.
On Wed, Jun 7, 2017 at 2:58 PM, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 下午2:44:21, Maxime Ripard
> 写到:
>>On Wed, Jun 07, 2017 at 08:47:18AM +0800, Icenowy Zheng wrote:
>>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>>
On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
wrote:
> On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
>> >
>> >
>> > 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>> >>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrot
于 2017年6月7日 GMT+08:00 下午2:48:55, Maxime Ripard
写到:
>Hi,
>
>On Wed, Jun 07, 2017 at 08:47:20AM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
>> contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
>> A
于 2017年6月7日 GMT+08:00 下午2:50:36, Maxime Ripard
写到:
>On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng
>wrote:
>> >
>> >
>> > 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>> >>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng
>wr
于 2017年6月7日 GMT+08:00 下午2:44:21, Maxime Ripard
写到:
>On Wed, Jun 07, 2017 at 08:47:18AM +0800, Icenowy Zheng wrote:
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>> new file mode 100644
>> index 00..af1a1d56c9
>> --- /dev
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