Hi!
Dne petek, 09. junij 2017 ob 18:51:02 CEST je Icenowy Zheng napisal(a):
> 于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard 写到:
> >On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> >> @@ -189,6 +211,8 @@ supported.
> >> >>
> >> >>
YouTube videos of
U.S. Congress money laundering hearing
of
Saudi Billionaire " Maan Al sanea"
with *bank of America*
and The owner of Saad Hospital and Schools
in the Eastern Province in *Saudi Arabia*
and the Chairman of the Board of Directors of Awal Bank in *Bahrain*
Previously I did not submit the patch to linux because of the missing
a83t's DT support of Linux...
And I saw Bananapi M3 haven't been supported for Linux, but for U-Boot.
Well, now I will try to fix up the a83t's DT support for Linux, and then
submitted it to uboot.
BTW, I found that the
- I have been using a cubietruck (cubieboard 3) for the last 3 years
booting it with a linux from micro SD card
- I had to replace the cubietruck and bought another cubietruck (cubieboard
3)
- it boots into android from nand and in cubie tools i can only select
"boot form nand" or "boot from
Hi,
Am 09.06.2017 um 17:36 schrieb Andre Przywara:
> On 09/06/17 16:26, Jagan Teki wrote:
>> On Friday 09 June 2017 08:21 PM, Maxime Ripard wrote:
>>> On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
+ {
+pinctrl-names = "default";
+pinctrl-0 = <_pins>,
于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard
写到:
>On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
>> >> @@ -189,6 +211,8 @@ supported.
>> >> Required properties:
>> >>- compatible: value must be one of:
>> >> *
Hi,
On Fri, Jun 09, 2017 at 09:24:19PM +0800, Ziping Chen wrote:
> From: Ziping Chen
>
> The SinA83T is an A83T core/daughter board combo from Sinlinx.
>
> Add support for it.
>
> Signed-off-by: Ziping Chen
> ---
> arch/arm/dts/Makefile
On Fri, Jun 9, 2017 at 11:08 AM, Chen-Yu Tsai wrote:
> On Thu, Jun 8, 2017 at 6:47 AM, Ilia Mirkin wrote:
>> On Wed, Jun 7, 2017 at 6:36 PM, Rob Herring wrote:
>>> On Fri, Jun 02, 2017 at 09:42:19PM +0200, Maxime Ripard wrote:
On Fri,
On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> @@ -189,6 +211,8 @@ supported.
> >> Required properties:
> >>- compatible: value must be one of:
> >> * allwinner,sun8i-v3s-de2-mixer
> >> +* allwinner,sun8i-h3-de2-mixer0
> >> +* allwinner,sun8i-h3-de2-mixer1
>
On Thu, Jun 8, 2017 at 6:47 AM, Ilia Mirkin wrote:
> On Wed, Jun 7, 2017 at 6:36 PM, Rob Herring wrote:
>> On Fri, Jun 02, 2017 at 09:42:19PM +0200, Maxime Ripard wrote:
>>> On Fri, Jun 02, 2017 at 06:10:24PM +0800, Chen-Yu Tsai wrote:
>>> > The MSI Primo81
The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery.
Enable the PMIC's battery power supply so the battery can be monitored.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 4
1 file changed, 4 insertions(+)
diff --git
Now that we have support for the AXP221 PMIC's USB VBUS detection and
DRIVEVBUS vbus control, we can use the USB OTG port in proper OTG mode.
This patch enables the aforementioned PMIC functions, adds the OTG ID
detection pin to the USB PHY node, and changes the mode of USB OTG to
"otg".
Hi,
On 09/06/17 16:26, Jagan Teki wrote:
> On Friday 09 June 2017 08:21 PM, Maxime Ripard wrote:
>> Hi Jagan,
>>
>> On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
>>> + {
>>> +pinctrl-names = "default";
>>> +pinctrl-0 = <_pins>;
>>> +status = "okay";
>>> +};
>>> +
>>>
On Friday 09 June 2017 08:21 PM, Maxime Ripard wrote:
Hi Jagan,
On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+_pins {
+ bias-pull-up;
+};
What is connected on that bus?
On Friday 09 June 2017 08:22 PM, Maxime Ripard wrote:
On Fri, Jun 09, 2017 at 01:03:56PM +, Jagan Teki wrote:
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64
On Fri, Jun 09, 2017 at 01:03:56PM +, Jagan Teki wrote:
> From: Jagan Teki
>
> NanoPi A64 is a new board of high performance with low cost
> designed by FriendlyElec., using the Allwinner A64 SOC.
>
> Nanopi A64 features
> - Allwinner A64, 64-bit Quad-core
Hi Jagan,
On Fri, Jun 09, 2017 at 12:40:52PM +, Jagan Teki wrote:
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + status = "okay";
> +};
> +
> +_pins {
> + bias-pull-up;
> +};
What is connected on that bus?
> + {
> + pinctrl-names = "default";
> +
On Wed, Jun 07, 2017 at 10:21:02PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 下午10:19:57, Maxime Ripard
> 写到:
> >On Wed, Jun 07, 2017 at 05:44:56PM +0800, Icenowy Zheng wrote:
> >> 于 2017年6月7日 GMT+08:00 下午5:43:43, Maxime Ripard
>
On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
> 在 2017-06-07 22:38,Maxime Ripard 写道:
> > On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > > >I have no idea what this is supposed to be doing either.
> > > >
> > > >I might be wrong, but I really feel like there's
Hi Jernej,
On Wed, Jun 07, 2017 at 08:15:12PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne sreda, 07. junij 2017 ob 16:38:27 CEST je Maxime Ripard napisal(a):
> > On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > > >I have no idea what this is supposed to be doing either.
> > > >
On Fri, Jun 09, 2017 at 02:38:39PM +0100, Andre Przywara wrote:
> Hi,
>
> On 09/06/17 13:40, Jagan Teki wrote:
> > From: Jagan Teki
> >
> > Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
>
> I think this is an artefact of the sun8i-dwmac merging,
Hi,
On 09/06/17 13:40, Jagan Teki wrote:
> From: Jagan Teki
>
> Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
I think this is an artefact of the sun8i-dwmac merging, where both David
and Maxime merged the DT patches in their trees (compare
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet
On Sat, Jun 03, 2017 at 12:24:22AM +0200, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jun 02, 2017 at 10:22:05AM -0400, David Miller wrote:
> > From: Maxime Ripard
> > Date: Fri, 2 Jun 2017 11:13:20 +0200
> >
> > > On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime
Hi,
On 09/06/17 13:27, Jagan Teki wrote:
> From: Jagan Teki
>
> NanoPi A64 is a new board of high performance with low cost
> designed by FriendlyElec., using the Allwinner A64 SOC.
>
> Nanopi A64 features
> - Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet
From: Jagan Teki
Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
Build error:
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dtb:
ERROR (duplicate_node_names): Duplicate node name /soc/ethernet@1c3
ERROR: Input tree has errors, aborting (use -f
From: Jagan Teki
NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.
Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet
From: Jagan Teki
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi
Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell
Date: Fri Jun 9 14:59:55 2017 +1000
Merge remote-tracking branch
On Mon, Jun 5, 2017 at 9:51 PM, Maxime Ripard
wrote:
> On Sat, Jun 03, 2017 at 10:44:24PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> This series adds support for the R_PIO pin controller on the A83T.
>> The pins managed this controller are mainly used for
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The A83T has 1 pingroup with 13 pins belonging to the R_PIO
> or special pin controller.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Linus Walleij
Pls funnel this through the ARM SoC
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The R_PIO on the A83T is almost the same as the one found on the A64,
> except that the CIR_RX function was moved from pin PL11 to pin PL12.
>
> Add a driver for it.
>
> Signed-off-by: Chen-Yu Tsai
Patch
On Sat, Jun 3, 2017 at 4:44 PM, Chen-Yu Tsai wrote:
> The R_PIO on the A83T is almost the same as the one found on the A64,
> except that the CIR_RX function was moved from pin PL11 to pin PL12.
>
> Add a compatible string for it.
>
> Signed-off-by: Chen-Yu Tsai
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