Allwinner V3s SoC has an Ethernet MAC and an internal PHY like the ones
in H3 SoC, however the MAC has no external *MII interfaces available at
GPIOs, thus only MII connection to internal PHY is supported.
Add this variant of EMAC to dwmac-sun8i driver.
The default value of the syscon
The EPHY control part of the EMAC syscon register has a bit called
CLK_SEL. On the datasheet it says that if it's 0 the EPHY clock is 25MHz
and if it's 1 the clock is 24MHz.
However, according to the datasheets, no Allwinner SoC with EPHY has any
extra xtal input pins for the EPHY, and the system
Allwinner V3s SoC has a syscon like the one in H3.
Add its compatible string.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/misc/allwinner,syscon.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but
have no external MII capability. That means that it can only use the
EPHY and cannot do Gbps transmission.
Add binding for it.
Signed-off-by: Icenowy Zheng
---
Allwinner V3s features an EMAC like the on in H3, but without external MII
interfaces, so being not able really to use RMII/RGMII.
And it has a different default value of syscon (0x38000 instead of 0x58000
on H3), which shows a problem that the EMAC clock freq should be 24MHz.
(Both H3 and V3s
From: Jagan Teki
Add initial support for Pine64 board with below features:
- U-Boot 2017.07-rc1
- Linux 4.11.5
- Default packages from buildroot
Cc: Andre Przywara
Signed-off-by: Jagan Teki
---
DEVELOPERS
From: Jagan Teki
Add initial support for bananapi M2 Plus board with below features:
- U-Boot 2017.07-rc1
- Linux 4.11.5
- Default packages from buildroot
Signed-off-by: Jagan Teki
---
DEVELOPERS | 1 +