On Wed, Jul 26, 2017 at 7:54 AM, Icenowy Zheng wrote:
>
>
> 于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard
> 写到:
>>On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote:
>>> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io
On 07/23, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> This patch utilizes the new PLL clk notifier to gate then ungate the
> PLL CPU clock after rate changes. This should prevent any system hangs
> resulting from cpufreq changes to the clk.
>
> Reported-by: Ondrej Jirman
On 07/23, Icenowy Zheng wrote:
> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
>
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX
于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard
写到:
>On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote:
>> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote:
>> > 在 2017-07-24 15:58,Maxime Ripard 写道:
>> > > On Sat, Jul 22, 2017 at
On 25 July 2017 at 16:36, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Jul 22, 2017 at 08:53:52AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun8i-h3 introduces a lot of changes to the i2s block such
>> as different
On Tue, Jul 25, 2017 at 04:29:52PM +0800, Chen-Yu Tsai wrote:
> default ARCH_SUNXI
> On Tue, Jul 25, 2017 at 3:47 PM, Maxime Ripard
> wrote:
> > Hi Chen-Yu,
> >
> > On Tue, Jul 25, 2017 at 01:09:16PM +0800, Chen-Yu Tsai wrote:
> >> The A80 is a
Hi,
On Sat, Jul 22, 2017 at 08:53:52AM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> The sun8i-h3 introduces a lot of changes to the i2s block such
> as different register locations, extended clock division and
> more operational modes. As we have to
On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote:
> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote:
> > 在 2017-07-24 15:58,Maxime Ripard 写道:
> > > On Sat, Jul 22, 2017 at 10:28:49AM +0800, Icenowy Zheng wrote:
> > > > Allwinner A64 SoC has an EMAC which is used to
Icenowy Zheng writes:
> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>
> Add the device tree binding of this chip, in order to make it possible
> to add this interrupt pin to device
BPi M64 has an AP6212 Wi-Fi/Bluetooth combo module, and the Wi-Fi SDIO
card is connected to the mmc1 controller.
The pwrseq of the mmc1 (used to reset the card) used to missing, and the
out-of-band interrupt line of the card is not specified.
Fix these issues for proper Wi-Fi support of BPi M64.
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed vdd-cpux constraints.
- Added
Banana Pi M64 connects the USB host-only controller on A64 SoC to a USB
hub, which provided the two USB Type-A ports on the board.
Enable the USB host controller.
The OTG function of the Micro-USB port needs the drivevbus function of
the AXP803 driver implemented, so it's not enabled now.
在 2017-07-25 16:29,Chen-Yu Tsai 写道:
default ARCH_SUNXI
On Tue, Jul 25, 2017 at 3:47 PM, Maxime Ripard
wrote:
Hi Chen-Yu,
On Tue, Jul 25, 2017 at 01:09:16PM +0800, Chen-Yu Tsai wrote:
The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of
default ARCH_SUNXI
On Tue, Jul 25, 2017 at 3:47 PM, Maxime Ripard
wrote:
> Hi Chen-Yu,
>
> On Tue, Jul 25, 2017 at 01:09:16PM +0800, Chen-Yu Tsai wrote:
>> The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
>> 1 cluster of 4 Cortex-A15s.
>>
Hi Chen-Yu,
On Tue, Jul 25, 2017 at 01:09:16PM +0800, Chen-Yu Tsai wrote:
> The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
> 1 cluster of 4 Cortex-A15s.
>
> This patch adds support to bring up the second cluster and thus all
> cores using the common MCPM code. Core/cluster power
On Mon, Jul 24, 2017 at 09:59:04PM +0800, Chen-Yu Tsai wrote:
> Now that we support the MMC controllers on the A83T SoC, we can enable
> them on some boards.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime
On Mon, Jul 24, 2017 at 09:59:05PM +0800, Chen-Yu Tsai wrote:
> The H8 homlet has a micro-SD card slot connected to mmc0,
> and onboard eMMC from FORESEE, connected to mmc2.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Thanks!
Maxime
On Mon, Jul 24, 2017 at 09:59:03PM +0800, Chen-Yu Tsai wrote:
> mmc2 can support 8-bit eMMC chips, with a dedicated reset line.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded
On Mon, Jul 24, 2017 at 09:59:02PM +0800, Chen-Yu Tsai wrote:
> The A83T has 3 MMC controllers. The third one is a bit special, as it
> supports a wider 8-bit bus, and a "new timing mode".
>
> Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
On Mon, Jul 24, 2017 at 09:58:58PM +0800, Chen-Yu Tsai wrote:
> The MMC2 clock supports a new timing mode. When the new mode is active,
> the output clock rate is halved.
>
> This patch sets the feature flag for the new timing mode, and adds
> a pre-divider based on the mode bit.
>
>
On Mon, Jul 24, 2017 at 09:58:56PM +0800, Chen-Yu Tsai wrote:
> Starting with the A83T SoC, Allwinner introduced a new timing mode for
> its MMC clocks. The new mode changes how the MMC controller sample and
> output clocks are delayed to match chip and board specifics. There are
> two controls
On Mon, Jul 24, 2017 at 09:58:57PM +0800, Chen-Yu Tsai wrote:
> All of our MMC clocks are of the MP clock type. A few MMC clocks on some
> SoCs, such as MMC2 on the A83T, support new/old timing mode switching.
>
> From a clock rate point of view, when the new timing mode is active. the
> output
On 25 July 2017 at 07:52, Maxime Ripard
wrote:
> Hi Markus,
>
> On Sat, Jul 22, 2017 at 08:53:51AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> In preparation for changing this driver to support newer SoC
>>
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