[linux-sunxi] [PATCH v5] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v5: - Added TODO's for PLL constraints. - Forced OHCI12M mux to 0. - Changed "adda" clock

[linux-sunxi] Re: [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

On Mon, Jul 24, 2017 at 7:46 PM, Rafael J. Wysocki wrote: > On Monday, July 24, 2017 02:23:49 PM Viresh Kumar wrote: >> On 23-07-17, 18:27, Icenowy Zheng wrote: >> > Some new Allwinner SoCs get supported in the kernel after the >> > compatibles are added to cpufreq-dt-platdev

Re: [linux-sunxi] [PATCH v6] arm64: allwinner: a64: Add initial NanoPi A64 support

On Tue, Aug 15, 2017 at 11:51 AM, Jagan Teki wrote: > On Tue, Aug 15, 2017 at 9:14 AM, Chen-Yu Tsai wrote: >> On Mon, Aug 14, 2017 at 6:36 PM, Jagan Teki wrote: [...] >>> +/* i2c1 connected with gpio headers like pine64,

[linux-sunxi] Re: [PATCH v3] arm64: allwinner: a64: Add A64-OLinuXino initial support

On Mon, Aug 14, 2017 at 6:46 PM, Jagan Teki wrote: > From: Jagan Teki > > OLimex A64-OLinuXino is an open-source hardware board > using the Allwinner A64 SOC. > > OLimex A64-OLinuXino has > - A64 Quad-core Cortex-A53 64bit > - 1GB or 2GB RAM

Re: [linux-sunxi] [PATCH v6] arm64: allwinner: a64: Add initial NanoPi A64 support

On Tue, Aug 15, 2017 at 9:14 AM, Chen-Yu Tsai wrote: > On Mon, Aug 14, 2017 at 6:36 PM, Jagan Teki wrote: >> From: Jagan Teki >> >> NanoPi A64 is a new board of high performance with low cost >> designed by FriendlyElec.,

Re: [linux-sunxi] [PATCH v6] arm64: allwinner: a64: Add initial NanoPi A64 support

On Mon, Aug 14, 2017 at 6:36 PM, Jagan Teki wrote: > From: Jagan Teki > > NanoPi A64 is a new board of high performance with low cost > designed by FriendlyElec., using the Allwinner A64 SOC. > > Nanopi A64 features > - Allwinner A64, 64-bit

Re: [linux-sunxi] Re: [PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

在 2017-08-15 10:16，Chen-Yu Tsai 写道： On Tue, Aug 15, 2017 at 12:53 AM, wrote: 在 2017-08-15 00:12，Chen-Yu Tsai 写道： )On Sat, Aug 12, 2017 at 8:43 PM, Icenowy Zheng wrote: Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond

Re: [linux-sunxi] Re: [PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

On Tue, Aug 15, 2017 at 12:53 AM, wrote: > 在 2017-08-15 00:12，Chen-Yu Tsai 写道： >> >> )On Sat, Aug 12, 2017 at 8:43 PM, Icenowy Zheng wrote: >>> >>> Allwinner R40 SoC have a clock controller module in the style of the >>> SoCs beyond sun6i, however, it's more

[linux-sunxi] Applied "ASoC: sun4i-i2s: Add clkdiv offsets to quirks" to the asoc tree

The patch ASoC: sun4i-i2s: Add clkdiv offsets to quirks has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to

[linux-sunxi] Applied "ASoC: sun4i-i2s: Add regmap config to quirks" to the asoc tree

The patch ASoC: sun4i-i2s: Add regmap config to quirks has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to

[linux-sunxi] Applied "ASoC: sun4i-i2s: Add TX FIFO offset to quirks" to the asoc tree

The patch ASoC: sun4i-i2s: Add TX FIFO offset to quirks has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to

[linux-sunxi] Re: [PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

在 2017-08-15 00:12，Chen-Yu Tsai 写道： )On Sat, Aug 12, 2017 at 8:43 PM, Icenowy Zheng wrote: Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng

[linux-sunxi] Re: [PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

)On Sat, Aug 12, 2017 at 8:43 PM, Icenowy Zheng wrote: > Allwinner R40 SoC have a clock controller module in the style of the > SoCs beyond sun6i, however, it's more rich and complex. > > Add support for it. > > Signed-off-by: Icenowy Zheng > --- > Changes in

[linux-sunxi] Re: [U-Boot] [PATCH] sunxi: defaultly enable SPL for Lichee Pi Zero

On Mon, Aug 14, 2017 at 8:30 PM, Icenowy Zheng wrote: > As we have already DRAM initialization code for V3s SoC, we can > defaultly enable SPL now on Lichee Pi Zero. > > Add CONFIG_SPL in Lichee Pi Zero defconfig. > > Signed-off-by: Icenowy Zheng Reviewed-by:

[linux-sunxi] [PATCH] sunxi: defaultly enable SPL for Lichee Pi Zero

As we have already DRAM initialization code for V3s SoC, we can defaultly enable SPL now on Lichee Pi Zero. Add CONFIG_SPL in Lichee Pi Zero defconfig. Signed-off-by: Icenowy Zheng --- configs/LicheePi_Zero_defconfig | 4 1 file changed, 4 insertions(+) diff --git

Re: [linux-sunxi] [PATCH v4 2/3] clk: sunxi-ng: nkm: add support for fixed post-divider

On Sat, Aug 12, 2017 at 8:43 PM, Icenowy Zheng wrote: > SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is > the fixed post-divider. > > Add post-divider support for NKM type clock. > > Signed-off-by: Icenowy Zheng > --- >

Re: [linux-sunxi] Re: [PATCH v4 1/3] clk: sunxi-ng: div: Add support for fixed post-divider

On Sun, Aug 13, 2017 at 10:50 AM, wrote: > 在 2017-08-12 20:43，Icenowy Zheng 写道： >> >> From: Priit Laes >> >> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where >> 6 is fixed post-divider. >> >> Signed-off-by: Priit Laes > > >

[linux-sunxi] [PATCH v3] arm64: allwinner: a64: Add A64-OLinuXino initial support

From: Jagan Teki OLimex A64-OLinuXino is an open-source hardware board using the Allwinner A64 SOC. OLimex A64-OLinuXino has - A64 Quad-core Cortex-A53 64bit - 1GB or 2GB RAM DDR3L @ 672Mhz - microSD slot and 4/8/16GB eMMC - Debug TTL UART - HDMI - LCD - IR receiver

[linux-sunxi] [PATCH v6] arm64: allwinner: a64: Add initial NanoPi A64 support

From: Jagan Teki NanoPi A64 is a new board of high performance with low cost designed by FriendlyElec., using the Allwinner A64 SOC. Nanopi A64 features - Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS - 1GB DDR3 RAM - MicroSD - Gigabit Ethernet

[linux-sunxi] Re: [PATCH] arm64: allwinner: a64: pine64: Use dcdc1 regulator for mmc0

Hi, On Sat, Aug 12, 2017 at 1:40 PM, Jagan Teki wrote: > From: Jagan Teki > > Since current tree support AXP803 regulators, replace > fixed regulator with AXP803 dcdc1 regulator. > > Tested on pine64. > > Signed-off-by: Jagan Teki

Re: [linux-sunxi] [PATCH 4/4] drivers: soc: sunxi: add support for A64 and its SRAM C

On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote: > Allwinner A64's display engine claims the SRAM C section to work. > > Add support for the A64 SRAM controller and the SRAM C section of it. > > Signed-off-by: Icenowy Zheng Looks good to me. Will apply all

Re: [linux-sunxi] [PATCH 3/4] drivers: soc: sunxi: add support for remapping func value to reg value

On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote: > On some Allwinner SoCs, sometimes the value needed to write into the > register to claim SRAM is not equal to the value specified in the > device tree. > > We now defines 0 as "CPU" and 1 as "Device", however, for VE SRAM,

Re: [linux-sunxi] [PATCH 1/4] dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C

On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote: > The display engine on Allwinner A64 wants to claim the SRAM C section. > > Add a SRAM controller compatible for A64, and a SRAM section compatible > for its SRAM C. > > Signed-off-by: Icenowy Zheng Looks

Re: [linux-sunxi] [PATCH v2] arm64: allwinner: a64: Add A64-OLinuXino initial support

On Mon, Aug 14, 2017 at 5:09 PM, Jagan Teki wrote: > On Mon, Aug 14, 2017 at 1:26 PM, Chen-Yu Tsai wrote: >> On Mon, Aug 14, 2017 at 3:34 PM, Jagan Teki wrote: >>> On Mon, Aug 14, 2017 at 12:38 PM, Chen-Yu Tsai

Re: [linux-sunxi] [PATCH v2] arm64: allwinner: a64: Add A64-OLinuXino initial support

On Mon, Aug 14, 2017 at 1:26 PM, Chen-Yu Tsai wrote: > On Mon, Aug 14, 2017 at 3:34 PM, Jagan Teki wrote: >> On Mon, Aug 14, 2017 at 12:38 PM, Chen-Yu Tsai wrote: >>> Hi, >>> >>> On Sun, Aug 13, 2017 at 1:54 AM, Jagan Teki

Re: [linux-sunxi] [PATCH v2] arm64: allwinner: a64: Add A64-OLinuXino initial support

On Mon, Aug 14, 2017 at 3:34 PM, Jagan Teki wrote: > On Mon, Aug 14, 2017 at 12:38 PM, Chen-Yu Tsai wrote: >> Hi, >> >> On Sun, Aug 13, 2017 at 1:54 AM, Jagan Teki wrote: >>> From: Jagan Teki >>> >>>

[linux-sunxi] Re: [PATCH 3/3] arm64: defconfig: Enable CONFIG_REGULATOR_AXP20X

On Sat, Aug 12, 2017 at 1:40 PM, Jagan Teki wrote: > From: Jagan Teki > > X-POWERS AXP20X PMIC Regulators is need for sunxi a64 > so make it default in defconfig. > > Signed-off-by: Jagan Teki Applied with the

Re: [linux-sunxi] [PATCH v2] arm64: allwinner: a64: Add A64-OLinuXino initial support

On Mon, Aug 14, 2017 at 12:38 PM, Chen-Yu Tsai wrote: > Hi, > > On Sun, Aug 13, 2017 at 1:54 AM, Jagan Teki wrote: >> From: Jagan Teki >> >> OLimex A64-OLinuXino is an open-source hardware board >> using the Allwinner A64 SOC.

[linux-sunxi] Re: [PATCH 1/3] bus: kconfig: Enable SUNXI RSB for arm64

On Sat, Aug 12, 2017 at 1:40 PM, Jagan Teki wrote: > From: Jagan Teki > > Sunxi arm64 doesn't have separate configs for > h5 and a64 so enable SUNXI_RSB bus for ARM64. The commit message is missing a lot of details. It assumes the reader

Re: [linux-sunxi] [PATCH v2] arm64: allwinner: a64: Add A64-OLinuXino initial support

Hi, On Sun, Aug 13, 2017 at 1:54 AM, Jagan Teki wrote: > From: Jagan Teki > > OLimex A64-OLinuXino is an open-source hardware board > using the Allwinner A64 SOC. > > OLimex A64-OLinuXino has > - A64 Quad-core Cortex-A53 64bit > - 1GB or 2GB

Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng wrote: > The pin controller of H5 has three IRQs at the chip's GIC, which > represents three banks of pinctrl IRQs. However, the device tree used to > miss the third IRQ of the pin controller, which makes the PG bank IRQ > not

Re: [linux-sunxi] [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng wrote: > The pin controller of Allwinner H5 has three IRQ banks, however in old > versions of drivers and device trees, only two are set, which makes > PG bank IRQ not available. > > If it's directly set to 3, the old device trees