On Samstag, 2. September 2017 00:32:50 CEST André Przywara wrote:
> Hi,
>
> On 01/09/17 02:19, Stefan Bruens wrote:
> > On Freitag, 1. September 2017 02:31:35 CEST Andre Przywara wrote:
> >> Hi,
> >>
> >> On 31/08/17 00:36, Stefan Brüns wrote:
> >>> The A64 SoC has the same dma engine as the H3 (
On Samstag, 2. September 2017 00:32:50 CEST André Przywara wrote:
> Hi,
>
> On 01/09/17 02:19, Stefan Bruens wrote:
> > On Freitag, 1. September 2017 02:31:35 CEST Andre Przywara wrote:
> >> Hi,
> >>
> >> On 31/08/17 00:36, Stefan Brüns wrote:
[...]
> >
> > For these 3 properties it likely is a
On 01/09/17 07:04, Maxime Ripard wrote:
> On Fri, Sep 01, 2017 at 01:31:35AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> On 31/08/17 00:36, Stefan Brüns wrote:
>>> The A64 SoC has the same dma engine as the H3 (sun8i), with a
>>> reduced amount of physical channels. Add the proper config data
>>> and
Hi,
On 01/09/17 02:19, Stefan Bruens wrote:
> On Freitag, 1. September 2017 02:31:35 CEST Andre Przywara wrote:
>> Hi,
>>
>> On 31/08/17 00:36, Stefan Brüns wrote:
>>> The A64 SoC has the same dma engine as the H3 (sun8i), with a
>>> reduced amount of physical channels. Add the proper config data
From: Philipp Rossak
* vqmmc is in this case not needed
* no need for pincontrol nodes when the pin is set to a GPIO
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m
From: Philipp Rossak
The WiFi side of the AP6212 WiFi/BT combo module is connected to
mmc1. There are also GPIOs for enable and interrupts.
Enable WiFi on this board by enabling mmc1 and adding the power
sequencing clocks and GPIO, as well as the chip's interrupt line.
Signed-off-by: Philipp Ro
From: Philipp Rossak
This is v2 of my Enable hardware for Nanopi M1 & Nanopi M1 Plus Patchseries.
Changes since v1:
- removed pincrtl node from power sequence
- removed vqmmc-supply
- changed ap6212 label to sdio_wifi
- removed vqmmc-supply & pincrtl node for powersequence on Bananap
On Freitag, 1. September 2017 15:35:49 CEST Maxime Ripard wrote:
> On Fri, Sep 01, 2017 at 05:04:54AM +0200, Stefan Bruens wrote:
> > On Donnerstag, 31. August 2017 16:51:35 CEST Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Thu, Aug 31, 2017 at 01:36:07AM +0200, Stefan Brüns wrote:
> > > > +/* Be
On Fri, Sep 01, 2017 at 05:04:54AM +0200, Stefan Bruens wrote:
> On Donnerstag, 31. August 2017 16:51:35 CEST Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Aug 31, 2017 at 01:36:07AM +0200, Stefan Brüns wrote:
> > > +/* Between SoC generations, there are some significant differences:
> > > + * - A2
On Mon, Aug 28, 2017 at 09:32:42AM +0300, Stefan Mavrodiev wrote:
> From revision J the board uses new phy chip LAN8710. Compared
> with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
> not to work. To fix this PA17 is muxed with GMAC function. This
> makes the pin output-low.
>
> This
On Thu, Aug 31, 2017 at 08:20:18AM +0300, Stefan Mavrodiev wrote:
> > > From revision J the board uses new phy chip LAN8710. Compared
> > > with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
> > > not to work. To fix this PA17 is muxed with GMAC function. This
> > > makes the pin outp
On Wed, Aug 30, 2017 at 11:51:37PM +0200, Philipp Rossak wrote:
> Hi,
> thanks for the feedback I will rework the patch.
> Should I also update the sun8i-h3-bananapi-m2-plus.dts? It uses also the
> AP6212 and it is done in the same way like in this patch.
Yes, please.
Maxime
--
Maxime Ripard, F
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